Tezzaron Semiconductor Corp.
| 1415 Bond St.
Naperville, IL, 60563-
|Firm CFO (or equivalent):|
|POC Contracting Officer (or equivalent)|
|SBC Control ID:|
Silicon-based detectors are central to all modern particle physics collider experiments. The functional area of these systems has increased from a few square centimeters in the mid-80s to 200 square m ...SBIR Phase I 2015 Department of Energy
ABSTRACT: Tezzaron proposes to create a microprocessor device based on an ARM M0 processor designed to be fabricated in the Honeywell S150 Rad-Hard SOI semiconductor process. The device will be desig ...SBIR Phase I 2014 Air ForceDepartment of Defense
ABSTRACT: ReRAM has made significant progress over the last few years and is ready for development by early adopters. Tezzaron proposes to create a multilayer 3D assembled ReRAM memory device using R ...SBIR Phase I 2014 Air ForceDepartment of Defense
ABSTRACT: Tezzaron proposes to develop and demonstrate a 64Mb 3D integrated MRAM device comprising one non-volatile memory cell layer and one radiation hardened I/O logic and control layer. This memo ...SBIR Phase II 2012 Department of Defense
ABSTRACT: Tezzaron intends to develop a nonvolatile low latency memory based on 3D assembly of RRAM memory cell wafers with CMOS logic wafers. The very high density 3D interconnect that Tezzaron can ...SBIR Phase I 2011 Department of Defense
Tezzaron proposes to use its 3D wafer stacking technology to produce a true 3 dimensional fabric of programmable logic. A benefit of 3D integration is the fundamental increase in interconnect. FPGAs b ...SBIR Phase I 2009 Air ForceDepartment of Defense
Chip-to-chip I/O has become a serious bottleneck, especially in communications between high-speed processors and their memory devices. Integrating a large amount of memory and a powerful processor int ...SBIR Phase II 2009 Air ForceDepartment of Defense
Tezzaron proposes to use and extend its 3D wafer stacking technology to produce a 8Gb DRAM. The device will be made from 8 layers of memory and a single logic control layer, providing density far beyo ...SBIR Phase I 2009 Defense Advanced Research Projects AgencyDepartment of Defense
Two radiation hardened 3D integrated circuit memory devices will be fabricated under this effort. The 3D devices are created by the wafer level 3D bonding of separate silicon substrates. Within each o ...SBIR Phase II 2009 Department of Defense
Tezzaron proposes the development of a 3D integrated memory on processor or host device. The proposed device is made from a very high-performance 3D integrated 512Mb DRAM memory device and a structure ...SBIR Phase I 2008 Air ForceDepartment of Defense