3-D Space Qualifiable Field Programmable Gate Array

Award Information
Agency:
Department of Defense
Amount:
$100,000.00
Program:
SBIR
Contract:
FA9453-09-M-0124
Solitcitation Year:
2008
Solicitation Number:
2008.3
Branch:
Air Force
Award Year:
2009
Phase:
Phase I
Agency Tracking Number:
F083-208-2721
Solicitation Topic Code:
AF083-208
Small Business Information
Tezzaron Semiconductor Corp.
1415 Bond St., #111, Naperville, IL, 60563
Hubzone Owned:
N
Woman Owned:
N
Socially and Economically Disadvantaged:
N
Duns:
844118195
Principal Investigator
 Robert Patti
 Systems Engineer
 (630) 505-0404
 david_taliaferro@mgtsciences.com
Business Contact
 Robert Patti
Title: President
Phone: (630) 505-0404
Email: kay_blemel@mgtsciences.com
Research Institution
N/A
Abstract
Tezzaron proposes to use its 3D wafer stacking technology to produce a true 3 dimensional fabric of programmable logic. A benefit of 3D integration is the fundamental increase in interconnect. FPGAs by their nature use huge amounts of interconnect and in normal 2D implementations, they often have an industry leading number of metal layers used. It has been well established that FPGAs operator slower than dedicated ASIC devices. Most of the added delay is in the interconnect fabric, not in the logic portion of the FPGA devices. Additional wiring resources could improve this situation, but the manufacturers are already pushing those limits, and adding more layers of metal interconnect does not ease the interconnect bottle necks at the logic source or destination. Given this set of facts, it seems obvious that a 3D FPGA with its larger number of potential interconnect solutions and the vertical commingling of wire with the logic should be able to significantly reduce the wiring fabric delays between logic elements.   Several new approaches to FPGAs are planned. These encompass yield improvement, enhanced speed, and more flexible interconnect. Another important aspect of this research is a new way to partition designs for place and route. This new method creates incremental and hierarical routing solutions that can accomodate specific FPGA device defects.   BENEFIT: The new approaches for FPGAs built in 3D that will be explored in this effort can be directly incorporated into future FPGAs by Tezzaron''''s collaborating partner, Xilinx. Further many of the paradigms can have applicability to other 3D circuits including SIP and SOC developments. The specific anticipated benefits include improved speed, lower power and lower cost for FPGAs. Improved radiation hardness is also anticipated from the 3D integration.

* information listed above is at the time of submission.

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