Design and Fabrication Techniques for 3-Dimensional Integrated Circuits

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$98,955.00
Award Year:
2009
Program:
SBIR
Phase:
Phase I
Contract:
W31P4Q-10-C-0012
Award Id:
91893
Agency Tracking Number:
09SB1-0146
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
1415 Bond St., #111, Naperville, IL, 60563
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
844118195
Principal Investigator:
Robert Patti
CTO
(630) 505-0404
rpatti@tezzaron.com
Business Contact:
Robert Patti
CTO
(630) 505-0404
rpatti@tezzaron.com
Research Institution:
n/a
Abstract
Tezzaron proposes to use and extend its 3D wafer stacking technology to produce a 8Gb DRAM. The device will be made from 8 layers of memory and a single logic control layer, providing density far beyond the capability of current commercial technology. A device of this density can offer significant improvements in system power, size, weight and performance. The major unknown in creating a device like this, are the issues that may arise when 3D integration is practiced beyond Tezzaron current devices of 3 or 4 tiers. In Phase I "dummy" wafers will be stacked to determine the feasibility of the planned 9 layer device to be fabricated as part of Phase II.

* information listed above is at the time of submission.

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