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Broadband Front Ends for Radar & Digital Receivers

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: N/A
Agency Tracking Number: 40262
Amount: $64,974.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1998
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
1080 Montreal Ave, Suite 200, St. Paul, MN, 55116
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Ross Smith
 () -
Business Contact
 Karl Fant
Phone: () -
Research Institution
 State University of New York
 Ivar Stran 
 Nonprofit college or university
Abstract
The Theseus Logic/SUNY-Stony Brook team is proposing to develop, demonstrate and commercialize Rapid Single Flux Quantum (RSFQ) circuit designed using NULL Convention Logic (NCL). Phase I of this program will demonstrate, by simulation and modeling, the feasibility of implementing logic gate structures in RSFQ technology which can exploi the effective delay insensitivity of NCL. In Phase II the team will build and demonstrate NCL-based RSFQ circuits for high-frequency broad band front ends for radar and communication digital receivers. Theseus Logic has developed and demonstrated the viability of a proprietary new logic family, NCL, which produces inherently clockless data driven, and effectively delay insensitive curcuits and systems. This technology produces circuit designs without concern for the detailed timing issues which make the prospects of global synchron-ization with clocks so difficult with frequencies in the 1-100 GHz range. Theseus is focused on the commercialization of its proprietary technology. The State University of New York at Stony Brook is a world leader in developing superconducting RSFQ device technology. RSFQ circuits have demonstrated the capability of LSI circuits running at clock speeds well above 100 GHz and power dissipation approaching four orders of magnitude less than CMOS

* Information listed above is at the time of submission. *

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