ADVANCED SIMULATION LANGUAGE FOR PROCESS MODELING AND PROCESS CONTROL IN METAL-WORKING

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$499,990.00
Award Year:
1985
Program:
SBIR
Phase:
Phase II
Contract:
n/a
Award Id:
1081
Agency Tracking Number:
1081
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
Universal Energy Systems Inc. (Currently UES, INC.)
4401 Dayton-xenia Road, Dayton, OH, 45432
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Sokka M. Doraivelu
(513) 426-6900
Business Contact:
() -
Research Institution:
n/a
Abstract
THIS PROPOSAL IS AIMED AT DEVELOPING A CONCEPT FOR IDENTIFYING A MODEL OF CONCURRENCY AND LANGUAGE TO DESCRIBE PARALLELISM INHERENT IN PROCESS SIMULATION (FINITE ELEMENT ANALYSIS) OF METAL-WORKING PROCESSES) AND PROCESS CONTROL. THE MAIN GOAL IS TO DEVELOP THE ADVANCED PARALLEL HARDWARE SYSTEMS TO (I) IMPROVE THE EXECUTION-TIME EFFICIENCY OF THE APPLICATION PACKAGES AND (II) CONTROL MATERIAL TESTING AND INDUSTRIAL PROCESSES IN METAL WORKING. THE APPROACH IS TO CAPTURE BOTH A MODEL OF CONCURRENCY AND LANGUAGE FOR DESCRIBIG CONCURRENT AND PARALLEL ALGORITHMS USING THE ALREADY DEVELOPED CONCURRENCY MODEL AD LANGUAGE BY TE INVESTIGATORS. DURING PHASE I, RESEARCH WILL BE DIRECTED TOWARDS IDENTIFYING CONCURRENT "PROCESSES" WHICH EXIST IN THE RIGID-VISCO-PLASTIC FEM APPLICATION SOFTWARE CALLED ANALYSIS OF LARGE PLASTIC INCREMENTAL DEFORMATION (ALPID) THAT HAS BEEN FULLY DEVELOPED AND VALIDATED UNDER BATTELLE COLUMBUS LABORATORIES - U. S. AIR FORCE PROCESSING SCIENCE PROGRAM FOR TWO DIMENSIONAL MATERIAL FLOW PROBLEMS. BASED ON THE CONCURRENCY MODEL, A LANGUAGE FOR DESCRIBING PARALLELISM WILL BE DEVELOPED. THE SAME PROCEDURE WILL BE FOLLOWED TO SOLVE PROBLEMS IN PROCESS CONTROL OF SLOW STRAIN RATE UPSETTING TEST/PROCESS. IN PHASE II, SOFTWARE SYSTEMS WILL BE DEVELOPED TO (I) TRANSLATE FROM HIGH-LEVEL EGINEERS' DESCRIPTIONS OF APPLICATION SOFTWARE INTO EXECUTALE PROCESS-GRAPH PROGRAMS AND (II) MAP FROM THESE PROCESS GRAPHS ONTO PARALEL HARDWARE FOR IMPROVING EXECUTION-TIME EFFICIENCY.

* information listed above is at the time of submission.

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