Next Generation Reconfigurable Field Programmable Gate Array

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$678,005.00
Award Year:
2010
Program:
SBIR
Phase:
Phase II
Contract:
FA9453-10-C-0022
Award Id:
93077
Agency Tracking Number:
F083-187-2379
Solicitation Year:
n/a
Solicitation Topic Code:
AF 08-187
Solicitation Number:
n/a
Small Business Information
6221 South Racine Circle, Centennial, CO, 80111
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
122032006
Principal Investigator:
BrettKoritnik
Principal Investigator
(303) 784-7706
brett.koritnik@seakr.com
Business Contact:
ScottAnderson
President & Co-Founder
(303) 790-8499
scott.anderson@seakr.com
Research Institute:
n/a
Abstract
The MAESTRO Phase II SBIR's focus is the design and build of a single board processor based on the MAESTRO chip developed by the U.S. Government. The board will be on a commercial VPX (Vita-46) 6U standard. The processor chip used on the board is a multi-core processor, with 49 identical processing cores, 4 banks of DDR2 memory, and 4 XAUI 10Gb interfaces. The VPX standard supports interfaces up to 40Gbps. The processor board will be designed as a prototype software development station for use by the MAESTRO community. The development includes an initial board support package, hardware and software documentation and porting of a software application from the phase I SBIR for validation of throughput. BENEFIT: The MAESTRO board has a number of applications, both terrestrial and space based. The initial prototype board will be used as a software development station for algorithmic development. The prototype board can be used as a verification vehicle for radiation testing and characterization of the MAESTRO processor itself. The board uses a powerful multi-core processor that has been developed using rad-hard by design libraries, and can be spun into a flight version for space applications.

* information listed above is at the time of submission.

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