MULTIDOMAIN ADAPTIVE SPACE/TIME PROCESSING AND SYSTOLIC ARRAYS

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$495,303.00
Award Year:
1989
Program:
SBIR
Phase:
Phase II
Contract:
n/a
Award Id:
8230
Agency Tracking Number:
8230
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
309 Curtis St, Syracuse, NY, 13208
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Donald R Miedaner
(315) 475-1121
Business Contact:
() -
Research Institution:
n/a
Abstract
THE OBJECTIVES OF THE PROPOSED PHASE I PROJECT ARE AS FOLLOWS: DEVELOP NEW ADAPTIVE SPACE/TIME ARCHITECTURES, APPLICABLE TO A FORWARD DPCA (ANTENNA MOVES NORMAL TO APERTURE PLANE), WHICH DEAL WITH JAMMING, CLUTTER, NARROWBAND INTERFERENCE, ERROR EFFECTS AND PLATFORM MOTION AS A SINGLE, INTEGRATED MULTIDOMAIN ADAPTIVE SPACE/ TIME PROCESS. THUS, ADAPTIVE SPACE/TIME TECHNOLOGY IS EXTENDED TO INCLUDE NOT ONLY THE ADAPTIVE SUPPRESSION OF JAMMING AND CLUTTER BUT ALSO THE ADAPTIVE CANCELLATION OF NARROWBAND UNINTENTIONAL INTERFERENCE, THE ADAPTIVE COMPENSATION OF ERROR EFFECTS IN THE ENVIRONMENT, ANTENNA AND RECEIVE CHANNEL AND ADAPTION TO SEVERE PLATFORM MOTION. DEVELOP THE ARCHITECTURE FOR A SYSTOLIC ARRAY DIGITAL PROCESSOR WHICH CAN PROVIDE THE REQUIRED PROCESSING POWER FOR IMPLEMENTING MULTIDOMAIN SPACE/TIME PROCESSING. GENERATE AN EXPERIMENTAL PLAN FOR PHASE II WHICH INCLUDES A SCALE-DOWN SYSTOLIC IMPLEMENTATION OF A MULTIDOMAIN ADAPTIVE SPACE/TIME PROCESSOR, WITH RF-TO-DIGITAL CONVERSION, AND A COMPUTER-DRIVEN WAVEOFRM EMULATOR BASED ON VECTOR MODULATION TECHNIQUES. THE PHASE I PROJECT WILL GENERATE AND USE A DETAILED COMPUTER MODEL WHICH WILL INCLUDE THE ENVIRONMENT (JAMMING SOURCES, CLUTTER, NARROWBAND INTERFERENCE AND TARGET RETURNS), THE ANTENNA (INCLUDING DISPERSIVE EFFECTS USING, AS REQUIRED, DETAILED ELECTROMAGNETIC MODELS), THE RECEIVE CHANNELS (CHANNEL MISMATCH ERRORS, DYNAMIC RANGE EFFECTS, ETC.) AND THE DIGITAL PROCESSOR (INCLUDING A/D CONVERSION, I/Q RESOLUTION AND SYSTOLIC ARRAY PROCESSING STRUCTURES).

* information listed above is at the time of submission.

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