Design-Hardened Radiation Tolerant Microelectronics

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-09-C-0013
Agency Tracking Number: F073-094-0591
Amount: $736,329.00
Phase: Phase II
Program: SBIR
Awards Year: 2009
Solicitation Year: 2007
Solicitation Topic Code: AF073-094
Solicitation Number: 2007.3
Small Business Information
2904 44th Avenue North, Saint Petersburg, FL, 33714
DUNS: 806504044
HUBZone Owned: N
Woman Owned: Y
Socially and Economically Disadvantaged: N
Principal Investigator
 Stephan Athan
 Chief Engineer
 (727) 547-9799
Business Contact
 Nancy Crews
Title: President
Phone: (727) 547-9799
Research Institution
This proposal describes an innovative reliability defect detection and fault propagation approach for improving integrated circuit reliability while minimizing impact on area overhead, power consumption, and electrical performance degradation over indigenous libraries. The approach is based on an innovative built in current sensor (BICS) technique designed to provide portability across process independent foundries suitable for digital, analog, and mixed signal design architectures. The BICS approach will be further characterized and validated against a standard set of metrics, including design, area overhead, performance, and power consumption, and further characterized as prototypes in silicon. Phase I included simulation and modeling of feasible designs, process variations, subthreshold leakage, radiation effects, and reliability monitor. These results provided baseline results for a Phase II research effort focusing on validating the theoretical results. A Phase II project will provide various detailed designs, layouts, and parts fabricated using a 180nm Bulk CMOS process to further validate the BICS solution set. The BICS designs will be used to determine its efficacy within a plug and play System Integrated Recovery (SIR) environment being developed by L-3/Jaycor, our collaborative partner. BENEFIT: Results from this successful research will lead to a cost effective reliability enhanced design (RED) technique for improving reliability of present and future space electronics, especially for space computers. Furthermore, the approach is ideally suited for present, as well as future, ultra large-scale integration (ULSI) integrated circuit (IC) designs based on ultra deep submicron processes. The technique overlays seamlessly in present day IC designs as a supplemental in-circuit reliability monitor for commercial and military electronics. The BICS possesses unique attributes enabling it to become increasingly more effective as circuit densities are increased and feature sizes scaled below 90nm making it ideal for plug and play architectures in operationally responsive space applications.

* Information listed above is at the time of submission. *

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