Chaos-Based Satellite Digital Communication System

Award Information
Agency:
Department of Defense
Branch
Army
Amount:
$69,960.00
Award Year:
2009
Program:
SBIR
Phase:
Phase I
Contract:
W15P7T-10-C-B407
Award Id:
92167
Agency Tracking Number:
A092-063-1215
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
500 E. Santa Anita Ave. #C, Burbank, CA, 91501
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
829498646
Principal Investigator:
Ashitosh Swarup
CEO
(818) 845-5820
aswarup@ashremtech.com
Business Contact:
Remy Ashe
COO
(310) 908-7301
rswarup@ashremtech.com
Research Institute:
n/a
Abstract
This proposal presents a methodology to develop a next-generation digital communication system that uses chaotic signals. The use of chaotic signals in digital communication systems offers several advantages. First, the noise-like properties of chaotic signals, both in their time- and frequency-domain representations, prevent them from being easily detected, giving greater immunity from eavesdropping and interception compared to spread-spectrum communication systems that use binary spreading sequences. Second, an infinite number of chaotic spreading waveforms can be generated, each with strong autocorrelation properties and weak cross-correlation properties; hence, a theoretically infinite number of users can be supported on a particular band, with minimum interference from other channels. Third, chaotic signals possess the salient features of broadband communication systems such as multipath mitigation and resistance to jamming. The proposed Phase I effort aims to analyze the feasibility of using chaotic signals in satellite digital communication systems through a software simulation approach. Three modulation/demodulation schemes will be programmed in MATLAB. Their performance will be evaluated under different criteria such as signal-to-noise ratio and the presence of jamming. These systems allow a straightforward hardware implementation for commercialization purposes; the hardware design steps are outlined as part of the proposed Phase I Option effort.

* information listed above is at the time of submission.

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