Testing Methodology/Tools for Asynchronous Circuits

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$749,627.00
Award Year:
2004
Program:
SBIR
Phase:
Phase II
Contract:
W31P4Q-04-C-R093
Agency Tracking Number:
02SB2-0328
Solicitation Year:
2002
Solicitation Topic Code:
SB022-045
Solicitation Number:
2002.2
Small Business Information
THESEUS LOGIC, INC.
12000 Research Parkway, Orlando, FL, 32826
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
940980113
Principal Investigator:
Lief Sorensen
Senior Engineer
(407) 282-9990
lief@theseus.com
Business Contact:
Ryan Jorgenson
VP Engineering
(407) 282-9990
rjorgenson@theseus.com
Research Institution:
n/a
Abstract
Theseus Logic, in partnership with FTL Systems, intends to integrate test and verification into their commercial design automation tool that will aid the designer by providing the means to automatically insert testability into clockless circuits. Success in this endeavor will eliminate one of the remaining obstacles that hinders widespread adoption of asynchronous design approaches for DoD and commercial applications. This proposal will involve the enhancement and integration of algorithms developed in Phase I as well as expanding the scope of the sub-circuits evaluated. It will also develop the framework necessary for performance analysis of NULL Convention Logic circuits. At the end of Phase II, the EDA tool commercially available from FTL Systems will have the following new features for support of clockless circuits: o The ability to seamlessly insert scan into a clockless design. o The ability to automatically generate a set of test vectors for the circuit. o The ability to measure the fault coverage from a set of test vectors. o The ability to support test vector generation by the TetraMAX ATPG tool.

* information listed above is at the time of submission.

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