Asynchronous Component Interconnect Protocol

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$69,443.00
Award Year:
2004
Program:
SBIR
Phase:
Phase I
Contract:
N00024-04-C-4137
Award Id:
69879
Agency Tracking Number:
N032-0804
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
3501 Quadrangle Blvd, Suite 100, Orlando, FL, 32817
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
940980113
Principal Investigator:
John Filion
Engineering Manager
(407) 282-9990
jfilion@theseus.com
Business Contact:
David Lamb
CEO and President
(407) 282-9990
dlamb@theseus.com
Research Institution:
n/a
Abstract
Theseus Logic, Inc. proposes a plug and play peripheral interconnect protocol that protects against obsolescence by using an asynchronous approach that does not rely on a specific clock rate. Additionally, an asynchronous approach provides robustness and flexibility that allows the same protocol used for a mezzanine bus to be applied to a peripheral bus. For this program, Theseus will apply their experience in chip level asynchronous interconnect techniques to the system level to develop a full featured interconnect architecture. This architecture will include the ability to support hardware information needed to maintain and calibrate the device, as well as version, manufacturer, description, and other data. Compatibility with current protocols will be retained to support legacy hardware.

* information listed above is at the time of submission.

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