Low Power GPS Signal Acquisition Using Asynchronous Logic

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$99,997.00
Award Year:
2006
Program:
SBIR
Phase:
Phase I
Contract:
FA9453-06-M-0145
Award Id:
78803
Agency Tracking Number:
F061-253-1780
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
12000 Research Parkway, Suite 436, Orlando, FL, 32826
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
940980113
Principal Investigator:
Michael Hagedorn
Senior Engineer
(407) 282-9990
hagedorn@theseus.com
Business Contact:
David Lamb
CEO
(407) 282-9990
dlamb@theseus.com
Research Institution:
n/a
Abstract
Achieving a new military GPS capability based on direct acquisition of P(Y) and M codes requires massive parallel processing with large numbers of correlator channels (>1000) in the receiver searching for a code match. In synchronous systems the extensive clock tree required to support a re-configurable, massively parallel architecture can burn half of the overall power of the processor. Theseus and Honeywell will solve this power problem with a data driven asynchronous design based on Theseus' Null Convention Logic (NCL) implemented in Silicon on Insulator (SOI) CMOS. Each block of data will be distributed to different correlators, individually correlated and averaged. The results of the asynchronous correlation will be combined and place in a clocked register that will integrate the asynchronous and synchronous elements of the system. Initially the power consumption of asynchronous and clocked designs of a small correlator bank will be compared using design methodologies and circuit analysis tools for NCL from the DARPA Clockless Logic Analysis, Synthesis and Systems (CLASS) program. The results will be extrapolated to Honeywell's innovative architecture that integrates GPS receiver processing with mitigation techniques for jamming, spoofing, multi-path and line of sight issues. The massively parallel correlator will be an extremely important enabling technology for this architecture.

* information listed above is at the time of submission.

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