Asynchronous Global Positioning Satellite (GPS) Baseband Processing Elements
Department of Defense
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Small Business Information
2524 Fairbrook Drive, Mountain View, CA, 94040
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AbstractThe Programmable Pipeline Array (PPA) is an asynchronous delay insensitive processor architecture implemented with NULL Convention Logic that is immune to Total Ionizing Dose radiation effects, and most Single Event Effects. The Theseus Research team will demonstrate the PPA's inherent radiation-hard properties, and will modify the PPA architecture to annunciate and recover from those few SEE's that affect correct operation, during this SBIR program. The PPA is a massively concurrent, instantly reconfigurable processor that provides a solution to the considerable computation needs of GPS. It processes flow graphs directly, expressing in hardware all of the concurrency inherent to the flow graph “program.” The PPA can nominally store 256 programs, any of which can be invoked during runtime with no loss of throughput. Theseus Research’s Invocation Language is the flow graph programming language used in conjunction with the PPA. The PPA provides GPS user equipment system designers with the power of hundreds of ASICs in one reconfigurable processor. It elevates the system design task to high level programming rather than low level ASIC design. It is a uniform hardware fabric that offers very high throughput, very low power and EMI, and which can be easily ported to new fabrication processes.
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