Radiation Hardened, Low Power Digital Signal Processors

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-04-M-0097
Agency Tracking Number: F041-020-0189
Amount: $99,900.00
Phase: Phase I
Program: SBIR
Awards Year: 2004
Solicitation Year: 2004
Solicitation Topic Code: AF04-020
Solicitation Number: 2004.1
Small Business Information
7902 NE St. Johns Rd., Bldg 102, Vancouver, WA, 98665
DUNS: 046546250
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Michael Fleming
 (360) 573-4084
Business Contact
 Michael Fleming
Title: President
Phone: (360) 573-4084
Email: mfleming@dsp24.com
Research Institution
An overdue standardized and programmable chip level approach will move Space based DSP into ultra-efficient frequency domain vector processing and allow high resolution, high sample rate, and multi-dimensional signal and image processing with minimal power dissipation and minimal software engineering. Current DSP processors take a "business" computing microprocessor architectural approach to DSP, ignoring the complex vector and data flow nature of digital signal processing applications. Our approach centers DSP around a unique multi-dimensional FFT centric structure that scales almost endlessly through cascading identical step and repeat macro library building blocks while maintaining signal precisions of 24 bits binary and beyond. By applying deterministic data flow techniques and a latency insensitive system approach our processors will efficiently maximize the final DSP resolution, precision, and sample rate of any chip geometry required by an application. Additionally, our chips can signal process "stand alone" or look like simple high level instruction set extensions to any host microprocessor, allowing the host to do what it does best simultaneously in parallel with the signal processing.

* Information listed above is at the time of submission. *

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