SBIR Phase I: A Novel Memory Having Both Volatile and Non-Volatile Modes For High Performance, Low Power Applications
National Science Foundation
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Small Business Information
Zeno Semiconductor, Inc.
1657 Curtner Ave, San Jose, CA, 95125-4920
Socially and Economically Disadvantaged:
AbstractThis Small Business Innovation Research (SBIR) Phase I project seeks to develop a novel memory, which has both volatile and non-volatile functionality. Such memory combines the non-volatile memory?s ability to retain information in the absence of power (such as Flash memory) and the fast access speed and reliability of a volatile memory (such as Static Random Access Memory (SRAM)). This memory is fabricated using a mainstream or near-production fabrication process and is a one-transistor device, which results in a compact cell size, suitable for cost-efficient high density applications. The proposed memory cell integrates a floating body transistor and a phase change memory element. During normal operation, the memory device functions as a floating body memory device and has SRAM-like performance, as in the access speed, power, and endurance capability. When power is removed from the memory device, the state of the floating body is saved into the phase change memory element by means of a mass, parallel, self-feedback mechanism. Subsequent to power restore, the original state of the floating body is recovered, also by means of a mass, parallel, self-feedback mechanism. The broader impact/commercial potential of this project is to enable power-efficient computing applications and mobile devices. For example, it can be used to reduce power consumptions in data centers. Data centers? annual energy consumption is estimated to be 150 billion kWh, about twice the capacity of the current US solar panel. A power-efficient memory such as the one proposed in this proposal can reduce the overall data centers? power consumption by up to 75%. Another application is to provide an integrated memory solution. Many electronic devices currently employ multiple types of memory, due to their own distinct characteristics. The proposed device will be able to combine the different types of memory into a single memory device.
* information listed above is at the time of submission.