High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX11CB14C
Agency Tracking Number: 094089
Amount: $599,934.00
Phase: Phase II
Program: SBIR
Awards Year: 2011
Solicitation Year: 2009
Solicitation Topic Code: S1.02
Solicitation Number: N/A
Small Business Information
AZ, Tucson, AZ, 85704-5645
DUNS: 157955597
HUBZone Owned: N
Woman Owned: Y
Socially and Economically Disadvantaged: N
Principal Investigator
 Principal Investigator
 (520) 742-3300
Business Contact
 Milena Thompson
Title: Business Official
Phone: (520) 520-3300
Email: milena@ridgetop-group.com
Research Institution
In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming (DBF) systems that will be used in NASA's future radar applications. The ADC will employ a novel combination of time interleaving, high-speed silicon-germanium BiCMOS technology and low-power techniques, such as the double-sampling technique, providing exceptional sampling speed of 500 MSPS, 1.5 GHz analog bandwidth,12 bits of resolution, and below 500 mW power dissipation, exceeding NASA's requirements.Ordinarily, ADC design requires large trade-offs in speed, resolution, and power consumption. The significance of this innovation is that it simultaneously provides a high-speed, high-resolution, and low-power ADC that is well ahead of the state of the art. These three characteristics are needed for DBF systems that contain large ADC arrays. The power consumption of existing ADC chips prohibits implementation of large DBF arrays in space. Ridgetop's innovative design leverages newer semiconductor process technologies that combine silicon and germanium into a compound semiconductor.Ridgetop has identified two Phase 2 objectives, which are:1. Design, fabricate and characterize Test Chip 1 that contains critical ADC subcircuits.2. Design, fabricate and characterize Test Chip 2 that contains the complete radiation tolerant, digitally calibrated, time-interleaved ADC design.During Phase 1 Ridgetop identified the topologies for all of the circuit blocks that will be included on Test Chip 1 and Test Chip 2. Ridgetop has also completed transistor-level designs for the key components on these chips.Estimated TRL at beginning and end of Phase 2 contract: Begin 4; End 8.

* Information listed above is at the time of submission. *

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