Accelerating ATM Optimization Algorithms Using High Performance Computing Hardware

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX11CD10P
Agency Tracking Number: 105968
Amount: $100,000.00
Phase: Phase I
Program: SBIR
Awards Year: 2011
Solicitation Year: 2010
Solicitation Topic Code: A3.01
Solicitation Number: N/A
Small Business Information
Optimal Synthesis, Inc.
CA, Los Altos, CA, 94022-2777
DUNS: 829385509
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Monish Tandale
 Principal Investigator
 (650) 559-8585
 monish@optisyn.com
Business Contact
 P. K. Menon
Title: Business Official
Phone: (650) 559-8585
Email: menon@optisyn.com
Research Institution
 Stub
Abstract
NASA is developing algorithms and methodologies for efficient air-traffic management (ATM). Several researchers have adopted an optimization framework for solving problems such as flight scheduling, route assignment, flight rerouting, nationwide traffic flow management and dynamic airspace configuration. Computational complexity of these problems have led investigators to conclude that in many instances, real time solutions are computationally infeasible, forcing the use of relaxed versions of the problem to manage computational complexity.The primary objective of this research proposal is to accelerate optimization algorithms that play central roles in NASA's ATM research, by parallel implementation on emerging high performance computing (HPC) hardware. The proposed research effort will first identify optimization algorithms that are key to achieving NASA's ATM research objectives. The effort will then explore various avenues for parallelizing the optimization algorithms, and focus on algorithms most amenable for implementation on HPC hardware. The feasibility of implementing one or more optimization algorithms, and potential for further acceleration will be demonstrated on ATM problems of sufficient complexity, which will then form the basis for the Phase II prototype. Phase II work will develop an operational prototype of the algorithm implementation on HPC hardware, and deliver them to NASA for further evaluation.

* information listed above is at the time of submission.

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