High Performance Ultra Low-Power ADCs and DACs

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX11CE01P
Agency Tracking Number: 105790
Amount: $99,964.00
Phase: Phase I
Program: SBIR
Awards Year: 2011
Solicitation Year: 2010
Solicitation Topic Code: O1.03
Solicitation Number: N/A
Small Business Information
4775 Centennial Boulevard, Suite 130, Colorado Springs, CO, 80919-3332
DUNS: 619085371
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Sasan Ardalan
 Principal Investigator
 (505) 294-1962
Business Contact
 Karen VanCura
Title: Business Official
Phone: (719) 531-0805
Email: karen.vancura@micro-rdc.com
Research Institution
The objective of the Phase-I research is to design a multi-GHz high bandwidth Delta Sigma Analog-to-Digital and Digital-to-Analog converter using a deep sub-micron CMOS process. Since the Delta Sigma Modulation ADC samples in the multi-GHz range, direct sampling and conversion to digital of post LNA Microwave signals is possible. By targeting the ADC on a CMOS technology node (90nm, 65nm or 45nm), a complete all digital radio receiver and demodulator can be implemented on the same System on a Chip that performs host interface and higher network level protocols. Using Delta Sigma Modulation at GHz sampling rates eliminates the anti-aliasing filter requirement. The all digital receiver eliminates I/Q imbalance due to the receiver and DC offset introduced by zero-IF architectures. In order to support multi GHz sampling rates in CMOS, advanced time interleaving, parallel Delta Sigma Modulators and shared integrator architectures are considered. Using Micro-RDC RHBD cells and design experience the digital filtering and decimation of the high frequency bit stream are hardened. The baseband filtering is implemented with temporal latch technology for SEU immunity. In this research various hardening techniques will be used to harden the analog sub-components in the Delta Sigma Modulator including investigating pipelining and parallel processing architectures for filtering and decimation which also address low power requirements.

* Information listed above is at the time of submission. *

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