1 Gb Radiation Hardened Nonvolatile Memory Development

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX11CH18P
Agency Tracking Number: 105782
Amount: $100,000.00
Phase: Phase I
Program: SBIR
Awards Year: 2011
Solicitation Year: 2010
Solicitation Topic Code: X6.02
Solicitation Number: N/A
Small Business Information
Scientic, Inc.
AL, Huntsville, AL, 35816-3440
DUNS: 826034550
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Jeff Dame
 Principal Investigator
 (256) 319-0860
Business Contact
 Gary Grant
Title: Vice President-Contracts
Phone: (256) 319-0858
Email: gary.grant@scientic.us
Research Institution
The objective of this effort is to identify, characterize and develop advanced semiconductor materials and fabrication process techniques, and design and produce a Gigabit (GB)-scale high density, radiation hardened (RH), SONOS-based nonvolatile memory (NVM) in a standard, high density CMOS technology with feature sizes approaching the 90nm technology node. Highly reliable, RH SWAP-efficient, high-density NVM provides for the deployment of more capable, flexible and responsive hardware designs leading to improved mission performance and enhanced data storage capability with less system operational complexity and reduced system vulnerability to natural and weapons generated radiation environments. By leveraging state-of-the-art (SOA) commercial NVM technologies and implementing a combination of these elements with the proper memory cell architecture, radiation hardened device design, and advanced fabrication processes, we are confident we can produce a 1Gb RH NVM using currently available CMOS process modules at or below the90 nm fabrication technology node. The unique materials and process technologies to be investigated in our approach include composite high-k dielectric thin-film oxide materials, shallow trench isolation, atomic layer deposition, p-channel silicon-insulator-nitride-oxide-silicon (SINOS) NVM architecture, and RH CMOS peripheral circuitry.

* information listed above is at the time of submission.

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