SOI CMOS Wafer Scale Imager Platform

Award Information
Agency:
Department of Energy
Branch
n/a
Amount:
$1,000,000.00
Award Year:
2011
Program:
SBIR
Phase:
Phase II
Contract:
DE-FG02-10ER85887
Award Id:
n/a
Agency Tracking Number:
94985
Solicitation Year:
2011
Solicitation Topic Code:
49 d
Solicitation Number:
DE-FOA-0000508
Small Business Information
15985 NW Schendel Avenue, Suite 200, Beaverton, OR, 97006-6703
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
124348652
Principal Investigator:
Adam Lee
Mr.
(971) 223-5646
adam@voxtel-inc.com
Business Contact:
George Williams
Mr.
(971) 223-5646
georgew@voxtel-inc.com
Research Institute:
Stub




Abstract
CMOS APS detectors have emerged as an attractive imaging solution to replace CCD technology. They can be very thin, yield good signaltonoise ratio (SNR) at room temperature, and offer the possibility of incorporating inpixel data processing. But despite its potential, APS has demonstrated relatively poor actual performance; a key reason is that in existing monolithic implementations, the photodiodes (PDs) are integrated into the same layer as the readout circuits, incurring tradeoffs in materials and pixel layout. An alternate approach using backside illumination (BSI) is becoming available, but present implementations have very little near infrared (NIR) response, making them illsuited for imaging night sky radiance. A commercial CMOS process is thus needed that can fabricate largearea, highpixeldensity, fully depleted BSI imagers, in a hybrid architecture. A highly NIRresponsive silicononinsulator (SOI) BSI imager technology is being developed, including: 1) lownoise CMOSbased readout circuits, 2) subfield photocomposition (stitched) fabrication, 3) thick, fully depleted PD arrays, and 4) vialess 3D wafer bonding and electrical interconnection. A highperformance SOI CMOS readout integrated circuit (ROIC) was characterized and optimized for 3D integration with deeply depleted silicon PD arrays. New pinned PD pixel layouts were designed, fabricated and demonstrated. The design met the solicited application specifications, including high quantum efficiency, response into the NIR, and overall lowlightlevel performance (dynamic range, uniformity, linearity, etc). An approach was developed for implementing the ROIC in a stitched form. The stitched ROIC pixel design was demonstrated in simulation and the PD devices were demonstrated through lab measurements on 10 mpitch arrays. The ROICs and PDs were made ready for largeformat array fabrication, 3D hybridization, and demonstration in working lowlightlevel cameras. In Phase II, the highdensity, largearea PD arrays will be optimized and readied for integration with the photocomposed ROIC. Existing ROIC wafers and PD array wafers will be hybridized using vialess wafertowafer bonding and electrical interconnection. Stitched largeformat ROICs will be fabricated on 200mm wafers and characterized, and these ROIC wafers will be hybridized to the PD arrays using the same bonding process. The stitched ROIC will be compared to its nonstitched predecessor. Imagers will be made available throughout for independent test and evaluation at DOE labs including LLNL. Commercial Applications and Other Benefits: In addition to lowlightlevel and persistent surveillance imaging, the technology has application in highenergy and nuclear physics, protein crystallography, DNA sequencing, electron microscopy, spectroscopy, spacequalified star trackers, astronomy, night vision, and other digital imaging applications.

* information listed above is at the time of submission.

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