Development of Commercial Foundry Source for Science-Grade Charged Particle Imagers

Award Information
Agency:
Department of Energy
Branch
n/a
Amount:
$1,000,000.00
Award Year:
2011
Program:
SBIR
Phase:
Phase II
Contract:
DE-FG02-10ER85961
Award Id:
n/a
Agency Tracking Number:
95098
Solicitation Year:
2011
Solicitation Topic Code:
44 d
Solicitation Number:
DE-FOA-0000508
Small Business Information
15985 NW Schendel Avenue, Suite 200, Beaverton, OR, 97006-6703
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
124348652
Principal Investigator:
George Williams
Mr.
(971) 223-5646
georgew@voxtel-inc.com
Business Contact:
George Williams
Mr.
(971) 223-5646
georgew@voxtel-inc.com
Research Institution:
Stub




Abstract
Domestic CMOS imager manufacturing technologies are attractive as a replacement for CCDs but do not yet meet all the requirements of scientific imagers. Their use in tailored scientific imaging applications is hampered by the large wafer sizes and high cost of deepsubmicron fabrication; the low voltage of standard processes also precludes the formation of deeply depleted photodiodes (PDs) in the same silicon as the readout circuits. Many new processes such as backside illumination (BSI) exist but are not optimized for sciencegrade imaging. Sciencegrade detectors would generally be best served by a 0.18m 6 & quot; CMOS fab, operating at production volume for quality, yield, and affordability. However, new processes such as substrate thinning, 3D integrated circuit stacking, and 3D via formation, as well as new packaging technologies, are available only on equipment for 8 & quot; and larger wafers. Ideally, in a sciencegrade imager, two separate silicon layers will be used to form the PDs and the readout circuits, allowing each to be formed in optimized silicon layers of two different resistivities. The use of silicon on insulator (SOI) CMOS wafers can accomplish this separation. A detectorinhandle (DH) BSI imager can be fabricated using the bottom (handle) Si layer of the SOI wafer to form PDs and the top Si layer to manufacture radhard, highspeed amplification and readout circuits. In this program, several steps are being added to a commercial CMOS process to support this architecture, most notably steps for the electrical interconnection between the PDs and the readout circuitry. The Phase I program demonstrated the feasibility of establishing a domestic, commercially available DHBSI imaging capability, for both 6 & quot; and 8 & quot; SOI CMOS wafers. Highperformance silicon photodetector arrays were fabricated on SOI wafers and characterized. An imager readout integrated circuit (ROIC) was fabricated on an 8 & quot; SOI process, and its optical and electrical performance was characterized. The process flow required to integrate the DHBSI on SOI CMOS processes was documented, and simulated using TCAD tools and prototypes. These processes were analyzed to prepare for porting to a 6 & quot; process. The throughBOX processes necessary to implement the DHBSI SOI CMOS imager will be optimized for a 6 & quot; domestic radiationhardened SOI CMOS process. After porting the ROIC from 8 & quot; to 6 & quot;, fabricating imagers, and confirming performance, fully functional DHBSI SOI CMOS imagers will be fabricated. The process flow will be prepared to port it to an 8 & quot; fab in the Phase III program. Commercial Applications and Other Benefits: The highperformance detector technology will enable innovation in markets from highenergy and nuclear physics detectors to military night vision and persistent surveillance, and industrial markets such as protein crystallography, optical and electron microscopy, astronomy, and highspeed imaging.

* information listed above is at the time of submission.

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