Wide Area Video Motion Blur Elimination

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$749,869.00
Award Year:
2010
Program:
STTR
Phase:
Phase II
Contract:
W31P4Q-10-C-0139
Award Id:
85007
Agency Tracking Number:
08ST1-0147
Solicitation Year:
2008
Solicitation Topic Code:
ST081-007
Solicitation Number:
2008.A
Small Business Information
11600 Sunrise Valley Drive, Suite # 290, Reston, VA, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
038732173
Principal Investigator:
JamesJacob
Principal Investigator
(703) 654-9300
fguo@objectvideo.com
Business Contact:
JamesJacob
VP, New Technology
(703) 654-9314
pbrewer@objectvideo.com
Research Institute:
BROWN UNIVERSITY
Darrell Armstrong
Box 1929
164 Angell Street
Providence, RI, 02912-
(401) 863-1430

Abstract
This Small Business Technology Transfer Phase-II project will design, develop and integrate an effective and efficient motion blur elimination algorithm to Autonomous Real-time Ground Ubiquitous Surveillance - Imaging System (ARGUS-IS) system by optimizing and implementing the algorithm proposed during the Phase-I investigation to FPGA. In addition, an image enhancement toolkit for ground station video enhancement will be developed. High performance parallel architectures will be investigated and designed to enable real-time operation of such a toolkit. The key innovations in the proposed effort are: 1) a novel efficient algorithm for non-Linear Shift-Invariant (LSI) motion blur elimination, and 2) an efficient and optimized FPGA implementation of the deblurring module for ARGUS-IS system. The Phase-II effort will build on the achievements of the Phase-I investigation in further refining and optimizing the proposed blur elimination algorithm with regard to both quality and computational complexity. In particular, emphasis will be on a real-time FPGA implementation of the algorithm to meet the system and integration requirements of the ARGUS-IS system. The Phase-II effort will include: development of the enabling algorithms, FPGA implementation, support for system integration, demonstration of the proof of concept, computational complexity analysis and quantitative evaluation of the proposed technologies.

* information listed above is at the time of submission.

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