Super Pixel Focal Plane Array Sensor

Award Information
Agency:
Department of Defense
Branch
Missile Defense Agency
Amount:
$749,780.00
Award Year:
2011
Program:
STTR
Phase:
Phase II
Contract:
W9113M-11-C-0017
Award Id:
n/a
Agency Tracking Number:
B2-1656
Solicitation Year:
2008
Solicitation Topic Code:
MDA08-T004
Solicitation Number:
2008.B
Small Business Information
5385 Hollister Ave, Suite 105, $749827, Santa Barbara, CA, CA, 93105-
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
16-720-20
Principal Investigator:
JohnCaulfield
Senior Engineer
(805) 453-0582
john@cyan-systems.com
Business Contact:
JohnCaulfield
Senior Engineer
(805) 453-0582
john@cyan-systems.com
Research Institute:
Research Triangle Institute
Gary Bulman
3040 Cornwallis Rd
Research Triangle Pa, NC, 27709-
(919) 541-9793

Abstract
In SFPA Phase I we developed a common ROIC that does not limit the performance of the emerging FPAs This ROIC uses a low noise input circuit and will facilitate direct comparison of the results obtained between different groups that may be using different SLS material combinations, unit cell designs or fabrication process, and especially different passivation approaches. The common platform will be designed to handle the current state of the art performance of MWIR and LWIR FPAs with surface leakage currents that range from values that dominate performance all way to the ideal case of being negligible in comparison to bulk limited diffusion currents. The ROIC will also operate with both g-r and diffusion current limited unit cells in situations with background fluxes from ambient f/2 to zero without dominating performance. The proposed approach offers a standard basic platform that is readily expandable to optimize performance for extreme regions of the parameter space such as very long wavelength operation that may require signal processing in the presence of very high thermal dark currents or background fluxes without resorting to very low FPA temperatures. A common ROIC will be available as a merchant supplied item with the potential for feature variation and customization without significant alteration to the basic circuit performance values. Feature variation includes array pitch and format (readily scalable to 1K x 1K or larger) as well as integration capacitor size.

* information listed above is at the time of submission.

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