Graphene synthesis on large-area silicon wafers suitable for manufacture
Department of Defense
Defense Advanced Research Projects Agency
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Small Business Information
Group 4 Development, LLC
3024 Hamilton Street, West Lafayette, IN, -
Socially and Economically Disadvantaged:
AbstractThis proposal investigates methods for graphene synthesis on Si (001) orientated substrates to enable high-volume production of graphene transistors and circuits. The proposed approach to generate a surface with the proper symmetry for graphene epitaxy is to deposit symmetry transformation layers (STL) of hexagonal-symmetry materials onto Si (001) substrates that will either facilitate the direct growth of graphene by physical vapor deposition methods, or the deposition of buffer layers upon which graphene is grown. A prototype deposition system is used in Phase I as a proof-of-concept instrument. All proposed processes are executed at temperatures of 1150 C or below so as to be compatible with existing Si technology. The proposed approach is innovative because it concentrates solely on the use of deposited layers, requires no smart cutting steps, and is suitable for manufacture. Phase I objectives are to (1) demonstrate graphene growth on Si (001) wafers, (2) demonstrate a functional symmetry transformation layer and, (3) establish conditions for graphene synthesis that will be applied in a larger deposition system for Phase II research and development. The Phase II objective is to grow graphene on 200 mm diameter Si (001) wafers that can serve as a commercial graphene materials product.
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