Incorporation of trust into integrated circuit (IC) and field programmable gate array (FPGA) design

Award Information
Agency:
Department of Defense
Branch
n/a
Amount:
$99,962.00
Award Year:
2011
Program:
SBIR
Phase:
Phase I
Contract:
W31P4Q-11-C-0158
Award Id:
n/a
Agency Tracking Number:
O102-A07-2108
Solicitation Year:
2010
Solicitation Topic Code:
OSD10-A07
Solicitation Number:
2010.2
Small Business Information
1245 Lyons Road, Building G, Dayton, OH, -
Hubzone Owned:
N
Minority Owned:
Y
Woman Owned:
N
Duns:
031764616
Principal Investigator:
Jorge Sanchez
Developer I
(937) 281-0783
j.sanchez@edaptive.com
Business Contact:
Praveen Chawla
President
(937) 281-0790
p.chawla@edaptive.com
Research Institute:
Stub




Abstract
As designs continue to progress in complexity, integration of third party assets has become a standard practice in hardware designs. Third party design integration, while reducing the complexity of the design process, always introduces risk in terms of the access to the internal components. These introduced elements are sometimes enclosed in a black-box, where system integrators cannot peek. Through the application of the VT-IP solution, we provide a framework for allowing more visibility and control over the functionality of integrated designs into FPGA hardware. The solution also provides a methodology for protecting critical device elements from adverse behavior in a third party design. The resulting capabilities will result in a marked increase in trust for FPGA integrators.

* information listed above is at the time of submission.

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