Single Event Transient Effects for Sub-65 nm Complementary Metal-Oxide Semiconductor (CMOS) Technologies
Department of Defense
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Small Business Information
Robust Chip Inc.
5820 Stoneridge Mall Rd., Suite 100, Pleasanton, CA, -
Socially and Economically Disadvantaged:
AbstractABSTRACT: Robust Chip (RCI) and Vanderbilt University (Vanderbilt) propose a joint project to create and characterize a comprehensive, accurate, single event simulation solution for ultra scaled (45nm, 32nm, and below) CMOS technologies. Development work on novel layout techniques for ultra deep submicron technologies will be integrated in this project as well, through the development of specific layouts and test structures to verify simulation accuracy in a 45nm (and below) technology. The simulation technology will be a very important building block in the design flow for a radhard designer, providing the fundamental information about single event behavior of the basic building blocks in the design. Furthermore, the technology supports RHBD layout methodology and the incorporation of RHBD techniques in layout synthesis tools. BENEFIT: The project focus is on developing a production strength single event analysis solution for 45nm, 28nm and 22nm CMOS, building on the most advanced single event characterization software available. The additional work on layout implementation and novel layout methodologies, will guide the development of the software solution both for qualification and calibration purposes, and for guidance on and adaption to, important target applications. The key innovations behind the technology in this project, the layout technology LEAP, and the new simulation methodology in accuro, originate in earlier DTRA and DARPA sponsored projects. The dedicated, unique simulation solution is of great strategic significance, providing an ability to accurately model effects that cannot be measured directly, reducing the very expensive and costly experimental testing (and possible re-designs), and providing a unique design support which will allow for the generation of the best possible radhard circuits and layouts with a minimum of performance penalty.
* information listed above is at the time of submission.