Radiation-Hardened, Deep-Submicron Application Specific Integrated Circuit
Small Business Information
Silicon Space Technology Corporation
3620 Lost Creek Boulevard, Suite 140, Austin, TX, -
AbstractABSTRACT: Silicon Space Technology (SST) proposes designing a customized 130nm Metal Programmable System on a Chip (MPSoC) slice based upon our 130nm fabric that can be used to implement multi-million gate designs. The slice would have embedded IP sub-circuits and IO interfaces that can be used to implement waveform digital processing designs. The MPSoC fabric uses SST"s Harden by Isolation (HardSIL) process solution that has been verified at the 130nm node with the 8M DP SRAM device. The HardSIL technology hardens against all the major radiation hard problems for both natural radiation environments Single-Event Effects (SEE), Total Ionizing Dose (TID), and Dose Rate (DR) for man-made radiation environments. SST would collect waveform digital processing requirements from defense prime contractors. Using these requirements, SST would design sub-circuits such as 24 bit multiply-accumulate circuits to be embedded as IP building blocks in the custom slice. SST would demonstrate that waveform digital processing circuits implemented using these embedded IP blocks in the custom slice would have significantly lower power and higher performance than is possible with an FPGA implementation. BENEFIT: Silicon Space Technology is developing and demonstrating multiple radiation-hardened client-based processes and products in a commercial foundry manufacturing environment through integration of our unique RH process modules which have been proven in silicon products. SST"s techniques are both patented and have other patents pending. SST"s HardSIL HBI technology mitigates Single-Event Effects (SEE) by significantly reducing the cross-section. HardSIL significantly increases Dose Rate (DR) threshold performance to>6.8E9 rad(Si)/sec, and can be tailored to increase Total Ionizing Dose (TID) performance beyond the Mrad level. The Company will use both government R & D and venture capital funding to further establish its RH technology at a commercial IC foundry to pervade the industrial electronics marketplace using the fabless"RH Client Process"model. Our multi-faceted fabless business/technical strategy is in its sixth year of commercialization, and we have been advised our innovations have progressed rapidly to a TRL = & #8805;6. The MPSoC slice to be studied under this Phase I proposal will utilize SST"s existing HardSil HBI process module enhancements targeted for high reliability and extreme operating environment market segments. HardSil has been successfully demonstrated to provide significant radiation hardening capabilities on several semiconductor products spanning several process technology nodes (250nm, 180nm, and 130nm). The MPSoC slice that will be developed under this proposal supports development for both commercial and military/space applications. SST is creating demand for this MPSoC slice technology through a dual-use strategy by working closely with prospective customers (including automotive, medical, power facility and down hole drilling equipment manufacturers as well as several contractors in the aerospace and military market segments). These customers are all typically confined to utilize older generation ASIC and/or specialty hardened IC products to meet their reliability needs (operation in industrial (and higher) and/or cryogenic operating temperatures, latch-up immunity, low single event upset rates, protection against total ionizing dose, etc. ). Historically, these companies have had to choose to sacrifice system performance for reliability. Customer defined MPSoC based circuits utilizing HardSIL technology would offer better system performance, be a less expensive, have faster time to market, and offer lower risk while maintaining the stringent requirements needed in these markets.
* information listed above is at the time of submission.