Development of an Ultra-Low Power IC Design and Packaging Technique to Provide a Variety of Critical Anti-Tamper Safeguards

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$99,998.00
Award Year:
2011
Program:
SBIR
Phase:
Phase I
Contract:
FA8650-11-M-1107
Agency Tracking Number:
F103-184-2690
Solicitation Year:
2010
Solicitation Topic Code:
AF103-184
Solicitation Number:
2010.3
Small Business Information
Space Photonics, Inc.
700 Research Center Blvd., Fayetteville, AR, -
Hubzone Owned:
Y
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
044870363
Principal Investigator:
Matthew Leftwich
Sr. Systems Engineer / COO
(479) 856-6367
mleftwich@spacephotonics.com
Business Contact:
Shonna Butler
Project and Finance Administrator
(479) 856-6354
sbutler@spacephotonics.com
Research Institution:
Stub




Abstract
Novel design methods, processes, and techniques, are needed including implementation demonstrations and subsequent security evaluations of alternative integrated circuit AT methods. These methods should provide multiple attributes of the following characteristics: a visible barrier to the underlying circuitry, electromagnetic shields to suppress or confuse radiated and conducted emissions, methods that protect from both the front and rear of the active integrated circuit areas, methods to detect intrusion and that initiate a tampering penalty, methods that cause the reverse engineering process to be substantially delayed or rendered fruitless. These techniques must be applicable to integrated circuit design and manufacturing processes, use minimal circuit area/power resources, provide minimal decrease in manufacturing yield, and remain cost effective. Advanced AT developments and techniques are required in the following integrated circuit areas: software/firmware design, circuit design, physical layout, and packaging techniques. Additionally, simulation and analysis methods need to be developed to assess and verify AT effectiveness, prior to fabrication. Test methods and measurement standards are required to assess the protection provided by the proposed mix of AT chosen for a particular point-design. This effort will therefore focus on developing innovative, ultra-low power IC design and packaging techniques that will provide a variety of die-level and package-level CPI/CT volume protection capabilities. BENEFIT: The proposed innovation will provide the following AT safeguards: i) Prevention of side-channel attacks (SCAs), including power-based, timing-based, electromagnetic (EM)-based, and fault-based ones; ii) Prevention of non-intrusive X-ray and SEM imaging with real-time knowledge (and triggering) of the imaging event; and iii) Prevention of physically de-packaging the IC with real-time knowledge (and triggering) of the de-packaging event. Applications are limited to critical military electronics that reqiure AT safeguards.

* information listed above is at the time of submission.

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