High Productivity, Robust FPGA Programming Tool

Award Information
Agency:
Department of Defense
Branch
n/a
Amount:
$148,250.00
Award Year:
2011
Program:
SBIR
Phase:
Phase I
Contract:
N68936-11-C-0032
Award Id:
n/a
Agency Tracking Number:
N111-014-0557
Solicitation Year:
2011
Solicitation Topic Code:
N111-014
Solicitation Number:
2011.1
Small Business Information
DSPlogic, Inc. (Currently DETECCA COMMUNICATIONS, INC.)
13017 Wisteria Drive, Suite 420, Germantown, MD, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
008171329
Principal Investigator:
Michael Babst
President
(301) 977-5970
mspb@dsplogic.com
Business Contact:
Michael Babst
President
(301) 977-5970
mspb@dsplogic.com
Research Institution:
Stub




Abstract
Field Programmable Gate Arrays (FPGA) are a very attractive, and often necessary, computational resource for intensive Digital Signal Processing (DSP) applications, including guidance systems. Their balance of performance, power consumption, and size make them ideally suited to SWAP-constrained sensor, communication, and guidance applications. However, the lengthy FPGA development and validation cycle, combined with limited application portability, contribute to relatively high life-cycle costs compared to modern embedded software systems. We propose the development of a high-level graphical programming environment for FPGA-based DSP applications. This model-based design environment, based upon object-oriented hardware design principles, will facilitate rapid FPGA system design by algorithm engineers across multiple platforms. Support for rapid integration and re-use of Intellectual Property (IP) cores is central to the proposed effort.

* information listed above is at the time of submission.

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