High Performance/Throughput, Low Latency and Low Power Field Programmable Gate Array (FPGA) for Software Defined Radio (SDR) and Cognitive Radio (CR)

Award Information
Agency:
Department of Defense
Branch
n/a
Amount:
$99,995.00
Award Year:
2011
Program:
SBIR
Phase:
Phase I
Contract:
W15P7T-11-C-H255
Award Id:
n/a
Agency Tracking Number:
A111-043-0165
Solicitation Year:
2011
Solicitation Topic Code:
A11-043
Solicitation Number:
2011.1
Small Business Information
5821 Sky Park Dr., Plano, TX, -
Hubzone Owned:
N
Minority Owned:
Y
Woman Owned:
Y
Duns:
828058508
Principal Investigator:
Nisha Checka
CEO/Founder
(617) 500-5481
nisha@goofyfootlabs.com
Business Contact:
Nisha Checka
CEO/Founder
(617) 500-5481
nisha@goofyfootlabs.com
Research Institution:
Stub




Abstract
FPGAs have become one of the most popular implementation media for digital circuits on account of their low NRE costs, field programmability, and time to market advantages over ASICs. However, FPGAs'greatest strength -- reconfigurability -- is also the source of their low performance and high power consumption. GoofyFoot Labs proposes the AMP 3D-FPGA, an innovative FPGA architecture, that achieves ASIC-like performance with significantly lower power consumption than conventional FPGA architectures. The AMP 3D-FPGA achieves 1.7-GHz peak performance while simultaneously reducing standby power consumption by 70% and dynamic power consumption by nearly 50% over other 65-nm FPGAs making it suitable for high performance and mobile domains. Additionally, the AMP 3D-FPGA provides added benefit to DoD applications because its innovative architecture improves its anti-tamper properties by making it more resilient to side-channel and fault attacks. In the Phase I program, GoofyFoot Labs will develop the AMP architecture and demonstrate its power and performance improvements.

* information listed above is at the time of submission.

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