Energy-Efficient Hierarchical FPGA and Programming Tools

Award Information
Agency:
Department of Defense
Branch
n/a
Amount:
$98,722.00
Award Year:
2011
Program:
SBIR
Phase:
Phase I
Contract:
W15P7T-11-C-A802
Award Id:
n/a
Agency Tracking Number:
A111-043-1257
Solicitation Year:
2011
Solicitation Topic Code:
A11-043
Solicitation Number:
2011.1
Small Business Information
15220 S Normandie Ave Unit 304, Gardena, CA, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
966299948
Principal Investigator:
ChengchengWang
Co-founder
(626) 991-9939
c2wang@hierlogix.com
Business Contact:
ChengchengWang
Co-founder
(626) 991-9939
c2wang@hierlogix.com
Research Institute:
Stub




Abstract
Today"s field-programmable gate array (FPGA) devices are expensive in size, power, performance, scalability and flexibility. The fundamental problem in these devices is the use of 2D-mesh interconnect architecture: it occupies large area, has long latency, consumes lots of power, and is not scalable. Interconnect takes more than 75% of the FPGA chip area. A large number of inactive transistors also produces significant leakage power (about 50% of the total FPGA power). Previous attempts in building hierarchical networks failed due to problems with routing congestion. HierLogix offers to develop a revolutionary FPGA technology consisting of FPGA hardware and supporting mapping tools. The proposed work is a radical departure from 2D-mesh design, which for N logic blocks has complexity O(N2), incomplete and heuristic routing. The proposed technology has only O(Nlog2N) complexity, complete and fully deterministic routing. It also has greatly reduced routing congestion compared to prior attempts in hierarchical networks, which makes the approach practical. We will specify architecture of FPGA and develop mapping tools to demonstrate FPGA technology that is 10x more energy-efficient than existing FPGAs.

* information listed above is at the time of submission.

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