Radiation Hardened Monolithic Heterogeneous Processors

Award Information
Agency: Department of Defense
Branch: N/A
Contract: HQ0147-12-C-7724
Agency Tracking Number: B2-1794
Amount: $999,998.00
Phase: Phase II
Program: SBIR
Awards Year: 2011
Solicitation Year: 2009
Solicitation Topic Code: MDA09-025
Solicitation Number: 2009.3
Small Business Information
100 Campus Drive, Marlborough, MA, -
DUNS: 78-091-71
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Steve Stecyk
 Director of Engineering
 (508) 658-7615
Business Contact
 Mark Beal
Title: CTO
Phone: (508) 658-7620
Email: mbeal@intrinsix.com
Research Institution
Future space tracking and surveillance systems are being required to provide ever-increasing sensor resolution and real-time processing of image data. What is needed is a flexible, high performance monolithic computing engine which is rad-hard to 300 krad (Si) and an architecture which is suitable for stream computing on real-time imaging data. Completed Phase 1 tasks, presented a heterogenous multi-processor system-on-chip architecture and performance modeling results that demonstrated a design that addresses these advanced requirements of space based acquisision and tracking applications. Phase II efforts will create a high level SystemC/TLM based model of the architecture giving payload designers the ability to simulate specific image processing algorithims and system trade-offs (# of simutaneous targets tracked, image resolution, frame rate). Design configuation tools will also be developed to automate the configuration design and verification process, allowing for rapid delivery of customizable compute platforms. Industry standard GPP, DSP, and on-chip interconnect fabric standards will be targeted to an IBM 45nm SOI process. Process selection, rad-hard-by-design cell library and logic design techniques will be used to create an initial RTL SoC designs.

* Information listed above is at the time of submission. *

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