High Performance, Ultra Low Power SPA-1 ASIC for Space Plug-and-Play Avionics
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AbstractABSTRACT: The Space Plug-and-play Avionics (SPA) initiative is designed to improve the ability of the US military to respond to rapidly changing operational needs by creating, integrating, and launching a new spacecraft in less than one week. This would provide major benefits to war fighters on the ground, in the sky, and at sea. SPA-1 ASICs using I2C as the transport interface will likely be the most proliferated endpoint for connection to the satellites"many sensors and actuators. Thus, the implementation of the SPA-1 ASIC must minimize size, weight and power without sacrificing performance. In Phase I, American Semiconductor demonstrated the ability to meet these needs by designing a high performance 50MHz, ultra low power, radiation-hardened SPA-1 ASIC processor core in the 130nm Flexfet double gate CMOS process. Operating at 0.5V, the Flexfet microprocessor core provides a 3X improvement in power over conventional bulk CMOS and a nearly 10X improvement in performance. In Phase II, American Semiconductor will design, manufacture and test Flexfet SPA-1 ASICs. This Phase II program will also provide an ASIC development platform and silicon proven building blocks for creation of other ultra low power, radiation-hardened ASICs in a US wafer foundry for use by DoD prime contractors. BENEFIT: There is a clear military requirement and desire for the technology to be developed under this Phase II SBIR. Space has become a contested environment in which it is critical for the US to have a clear technology advantages. The Space Plug-and-play Avionics (SPA) initiative is part of the Operationally Responsive Space goal of reducing the time from identification of a mission need to fielding an operationally capable satellite. The importance of the SPA initiative was recently recognized by being named the 2010 Hot Technology Contest Winner for the Air Force. In addition, AFRL has sponsored a number of SPA programs and a key driver in the development of the SPA standards. For the Air Force to fully benefit from the SPA initiative, new microelectronics that implement the SPA protocols and standards must be developed to address the low power, high performance and radiation tolerance requirements of space. SPA-x ASICs are fundamental building blocks for development of these plug-and-play satellites. SPA-1 uses the I2C transfer protocol and is envisioned by satellite designers as the"leaves on the tree", or most numerous SPA ASIM component, for connection to the multiple sensors and actuators employed on the plug-and-play satellites. The current start-of-the-art for SPA-1 is implementation in a structured ASIC. A structured ASIC is a good approach for development, but cannot meet the low power and performance specifications or mixed-signal capability developed in this program. Dramatic breakthroughs in the area of low power electronics is crucial for continued advancement in radiation-hardened electronics for space and military applications. Under this SBIR Phase II program, American Semiconductor will deliver SPA-1 ASICs built in the 130nm Flexfet CMOS technology to significantly reduce the size, weight, and power when compared to using the existing structured ASIC implementation. Operating at 0.5V, a SPA-1 ASIC in the double-gate Flexfet CMOS technology will provide a 3X improvement in power over conventional bulk CMOS and a nearly 10X improvement in performance while also providing inherent tolerance to radiation. The power and performance breakthroughs to be demonstrated under this proposal are also needed across a wide spectrum of commercial applications that include medical, distributed networks, and energy scavenging sensors, to name just a few. This approach must be successfully commercialized to insure technology availability to defense programs, provide a stable supply base, and benefit from on-going development to sustain the technology. American Semiconductor has a demonstrated track record supplying and supporting new technology as demonstrated by the company"s selection as the 2007 Supplier of the Year Award for Technology from Boeing Corp. The commercialization potential for this SBIR is along two paths. The first commercialization opportunity from this proposal will be to market the Flexfet SPA-1 ASIC to both military and commercial satellite manufacturers. Success of the Flexfet SPA-1 prototype will lead to development of more complex SPA-x variants such as the SPA-U USB and SPA-S Spacewire variants. The second path is providing the Flexfet ULP CMOS process as a foundry offering to satellite and IC designers that need to conserve system power. This has multiple sub-areas of commercialization such as foundry wafer sales, IP block licensing, and follow-on derivative product development and sales. Along the second commercialization path, the first product to leverage the technology from this SBIR will be IP blocks in Flexfet CMOS complementary to the SPA-1 ASIM, such as SRAM, ADCs, and I2C interface. These IP blocks allow designers to immediately utilize Flexfet CMOS to design ULP ICs that can further size, weight, and power (SWaP) advantages in satellite and other low power systems. Success in this area will enable further development of IP blocks, which leads to faster, lower cost development of future ICs through the use of IP blocks proven in silicon and available to designers working with Flexfet. The technology from this proposal will require little additional funding to bring to market. Flexfet CMOS is in place and being used by customers today. The SPA-1 ASIC developed in this program is anticipated to meet datasheet requirements such that silicon can be immediately started to fulfill customer demand for initial development. Qualification and reliability testing for both commercial terrestrial and military space applications can proceed in parallel with delivery of initial prototypes. Marketing and advertising expense will be necessary, but will leverage existing company efforts as much as possible.
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