3D Memristor Architectures for Software Defined Radio

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N66001-11-C-5212
Agency Tracking Number: N093-222-0984
Amount: $749,956.00
Phase: Phase II
Program: SBIR
Awards Year: 2011
Solitcitation Year: 2009
Solitcitation Topic Code: N093-222
Solitcitation Number: 2009.3
Small Business Information
Privatran
1250 Capital of Texas Highway South, Building 3, Suite 400, Austin, TX, -
Duns: 788622012
Hubzone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Burt Fowler
 Principal Investigator
 (512) 431-8460
 burt@privatran.com
Business Contact
 Glenn Mortland
Title: CEO / President
Phone: (512) 633-3476
Email: gmortland@austin.rr.com
Research Institution
 Stub
Abstract
PrivaTran proposes the use of newly-developed manufacturing methods that convert materials commonly found in conventional integrated circuit (IC) manufacturing into memristor devices with increased packing density and an advanced, three-dimensional (3D) architecture. The memristor devices can be formed in the interconnect layers of a conventional IC so that the area available for underlying transistors is not affected. This approach results in a 3D architecture achieved using a single substrate without the need for bonding multiple die together with flip-chip or through-silicon-via technologies. Furthermore, the memristor devices are much smaller than single transistors for any given technology node, and will scale to smaller dimensions as IC technology continues to progress towards smaller and smaller transistor sizes. The two-terminal memristor devices have numerous advantages including on/off conductance ratios greater than 104, reversible and fast switching, long retention times and immunity to current-induced degradation. In addition, their inherent simplicity makes them highly compatible with Si-based microelectronics technology, leading to a 3D architecture that can be readily transferred into semiconductor products at the most basic, integrated circuit level.

* information listed above is at the time of submission.

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