Processor Architectures for Multi-Mode Multi-Sensor Signal Processing

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$497,764.00
Award Year:
2011
Program:
SBIR
Phase:
Phase II
Contract:
N68335-11-C-0394
Agency Tracking Number:
N101-023-0594
Solicitation Year:
2010
Solicitation Topic Code:
N101-023
Solicitation Number:
2010.1
Small Business Information
RDRTec Inc.
3737 Atwell St., Suite 208, Dallas, TX, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
611827812
Principal Investigator:
Sidney Theis
President
(214) 213-5579
sidtheis@rdrtec.com
Business Contact:
Sidney Theis
President
(214) 213-5579
sidtheis@rdrtec.com
Research Institution:
Stub




Abstract
RDRTec Inc. and SAIC propose to develop and test innovative processor architectures for Maritime Classification Aids (MCA) and Sense And Avoid (SAA) algorithms. MCA algorithms include ship classification and Automatic Target Recognition (ATR) for both stand-alone Inverse Synthetic Aperture Radar (ISAR) images and fusion with simultaneous EO/IR sensor images when available. SAA algorithms include radar signal processing, tracking, and avoidance in a multiple threat environment. Feature extraction, fusion and ATR algorithms are data intensive parallel signal processing applications. The commercial graphics and gaming industry are leading the way in a new class of general purpose graphics processors units (GPGPU). Many core processing architectures are now available for size, weight, power, and cost (SWaP-C) constrained DoD platforms. For data intensive parallel signal processing applications, computational performance improvements of 10x to 100x over current digital signal processing (DSP) implementations have proven achievable.

* information listed above is at the time of submission.

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