Automated Generation of Advanced Test Diagrams to Reduce Test Program Set Life-Cycle Costs

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N68335-11-C-0198
Agency Tracking Number: N101-029-2230
Amount: $1,194,420.00
Phase: Phase II
Program: SBIR
Awards Year: 2011
Solicitation Year: 2010
Solicitation Topic Code: N101-029
Solicitation Number: 2010.1
Small Business Information
4266 Linda Vista Dr., Fallbrook, CA, -
DUNS: 833074904
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Ronald Taylor
 Chief Technologist
 (760) 310-5916
Business Contact
 Ronald Taylor
Title: Chief Technologist
Phone: (760) 310-5916
Research Institution
The objective of this Phase II research project is to develop a process and associated tools to generate wiring test diagrams automatically using data compliant with the IEEE Automatic Test Markup Language (ATML) family of standards. Test diagrams show the routing of signals from instruments to Unit Under Test (UUT) pins for each test in an automatic test program which tests a UUT on an Automatic Test Equipment (ATE) and are extremely useful in the troubleshooting of a Test Program Set (TPS). Automating the test diagram generation process will decrease the lengthy time to generate test diagrams by eliminating many hours of analysis of test stations, test programs and associated interface hardware. The Phase I study identified methods to use ATML data to generate test diagrams which provides a much desired open systems approach and will be employed in Phase II. Phase II work will also consist of producing ATML development tools for the ATML Test Station and Test Adapter to assist in the generation of ATML instance files, the resultant files will be used as an input to the test diagram tool. Phase I demonstrated that ATML support tools are essential for cost effective implementation of the ATML standards.

* Information listed above is at the time of submission. *

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