Operating System Mechanisms for Many-Core Systems

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8750-12-C-0172
Agency Tracking Number: O11B-T04-1015
Amount: $99,966.00
Phase: Phase I
Program: STTR
Awards Year: 2012
Solicitation Year: 2011
Solicitation Topic Code: OSD11-T04
Solicitation Number: 2011.B
Small Business Information
101 Bel Aire Dr, Monroeville, PA, 15146-
DUNS: 969081533
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Raj Rajkumar
 (412) 607-6404
Business Contact
 Raj Rajkumar
Title: President
Phone: (412) 607-6404
Email: raj@timecaptain.com
Research Institution
 Carnegie Mellon University
 Leslie Levine
 5000 Forbes Ave
Pittsburgh, PA, 15213-
 (412) 268-8722
 Nonprofit college or university
Overwhelming heat and clocking considerations have led to the accelerating rise of multicore processors. The number of cores per chip is expected to increase rapidly in coming years. In fact, chips with 100 cores and prototypes with 128 cores are already available. As the number of cores increases, the scalability of the operating system(s) will become a major bottleneck, particularly for embedded real-time systems where both performance and predictability are critical. We propose a suite of real-time operating system extensions that will (a) significantly enhance their scalability by minimizing inter-core OS data sharing, (b) explicitly limit migration of real-time tasks across cores, (c) automatically split a small number of selected tasks across two proximate cores for maximizing schedulable utilization, (d) perform admission control and resource reservation to offer both spatial and temporal isolation across applications. A functioning prototype on a real-time operating system will showcase some of these capabilities.

* Information listed above is at the time of submission. *

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