A 45 nm Low Cost, Radiation Hardened, Platform Based Structured ASIC

Award Information
Agency:
National Aeronautics and Space Administration
Branch
n/a
Amount:
$124,926.00
Award Year:
2012
Program:
SBIR
Phase:
Phase I
Contract:
NNX12CE35P
Agency Tracking Number:
114900
Solicitation Year:
2011
Solicitation Topic Code:
S3.01
Solicitation Number:
n/a
Small Business Information
American Semiconductor, Inc.
3100 South Vista Avenue, Suite 230, Boise, ID, 83705-0230
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
076338677
Principal Investigator:
William Tiffany
Principal Investigator
(208) 336-2773
billtiffany@americansemi.com
Business Contact:
Lorelli Hackler
Chief Financial Officer
(208) 336-2773
lhackler@americansemi.com
Research Institution:
Stub




Abstract
The proposed 45 nm radiation hardened platform based structured ASIC architecture offers the performance and density expected of a custom ASIC with the low manufacturing cost associated with a structured ASIC. The low cost, high performance customization of the structured ASIC portion of the chip is made possible by the 1-D 45 nm Mask-Lite process technology. The chip architecture is optimized for sensor data handling applications in space and the design process provides for a short development schedule. The architecture provides a hard macro microcontroller core with via-ROM program memory, SRAM data memory, CPU support logic, an appropriate set of analog functions, and a structured ASIC section for application specific functionality. A rad-hard by design logic cell library is provided for the structured ASIC area of the die along with a number of pre-compiled macro functions such as timers and serial I/O to reduce development time. The 1-D Mask-Lite process provides a dramatic reduction in the mask cost, allowing lower volume designs to gain access to 45 nm technology, and provides performance improvement over conventional via mask structured ASIC technologies by eliminating metal layer stubs. Standard logic design, verification and layout EDA tools are used to complete a chip design. The fixed microcontroller platform portion of the chip is implemented with optimized standard cells rather than the structured ASIC logic cells, resulting in standard ASIC performance levels for the core logic.

* information listed above is at the time of submission.

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