Low-power Cross-Correlator ASIC

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX12CE50P
Agency Tracking Number: 115685
Amount: $124,971.00
Phase: Phase I
Program: SBIR
Awards Year: 2012
Solicitation Year: 2011
Solicitation Topic Code: S1.03
Solicitation Number: N/A
Small Business Information
CA, Culver City, CA, 90230-4650
DUNS: 831566877
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Denis Zelenin
 Principal Investigator
 (310) 683-2628
Business Contact
 Dalius Baranauskas
Title: Business Official
Phone: (310) 683-2628
Email: dalius@pacificmicrochip.com
Research Institution
Pacific MicroCHIP Corp. offers to design an ASIC that includes a cross-correlation unit together with the interfaces to be connected to the output of the GeoSTAR's receivers, multiplexer and output interface for the GeoSTAR's system-level integration. The proposed novel ASIC required by NASA's PATH mission will have a greatly reduced power consumption compared to a FPGA based or a classic ASIC based implementations, increased radiation hardness and extended operating temperature range. The proposed cross-correlation unit consists of cross-correlation cells which are based on novel architecture. The logic primitives are arranged to "work when must" rather than to "work when need" in these novel cross-correlation cells. The high speed interfaces the proposed ASIC will incorporate can minimize the power consumption and increase the reliability. Termination resistors, amplifiers, analog-to-digital-converters realized inside the ASIC will save power due to shorter interconnects compared to interconnects that are used in FPGAs. Moreover, the high-speed receivers-deserializers could further save the power due to reduced number of termination resistors compared to the high-speed interface with analog-to-digital converters. The deep submicron SOI CMOS technology selected for the ASIC's fabrication will increase its tolerance to total ionizing dose (TID) and reduce the probability of radiation induced latch-up. The ASIC will be designed following the design for testability (DFT) methods that will simplify characterization and testing of the fabricated ASIC thus will reduce the risk and lower the cost of the product.Phase I of the project will provide a complete definition of the proposed ASIC, its design and in silico validation of critical circuits. Phase II will produce a fieldable product ready for commercialization in Phase III.

* Information listed above is at the time of submission. *

Agency Micro-sites

SBA logo
Department of Agriculture logo
Department of Commerce logo
Department of Defense logo
Department of Education logo
Department of Energy logo
Department of Health and Human Services logo
Department of Homeland Security logo
Department of Transportation logo
Environmental Protection Agency logo
National Aeronautics and Space Administration logo
National Science Foundation logo
US Flag An Official Website of the United States Government