Multi-Channel Time-to-Digital Converter for Pulse Shape Analysis

Award Information
Agency:
Department of Energy
Branch:
N/A
Amount:
$150,000.00
Award Year:
2012
Program:
SBIR
Phase:
Phase I
Contract:
DE-FG02-12ER90356
Agency Tracking Number:
99396
Solicitation Year:
2012
Solicitation Topic Code:
33 b
Solicitation Number:
DE-FOA-0000577
Small Business Information
Advanced Science And Novel Technology Company
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275-7848
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
114422095
Principal Investigator
 Vladimir Bratov
 Dr.
 (310) 377-6029
 vbratov@adsantec.com
Business Contact
 Vladimir Katzman
Title: Dr.
Phone: (310) 377-6029
Email: vkatzman@adsantec.net
Research Institution
 Stub
Abstract
Robust reconfigurable high-accuracy time-to-digital converters (TDCs) are required for next generation nuclear physics experiments, as well as existing system upgrade, such as particle identification in Time-of-Flight detectors, particle tracking in gas-based drift detectors, and BaF2 detectors in particular. Our company proposes to develop a novel, multi-channel time interval digitizing system- on-chip with integrated user-selectable pulse-preprocessing sampling circuitry that incorporates up to k=8 time digitization channels with about 5ps accuracy per channel and provides a possibility to register up to k sampling pints on the input pulse. The systems break-through performance will be achieved through the utilization of the companys proprietary patent pending TDC architecture and the unique silicon-proved CML library of basic cells and functional blocks that includes high-speed comparators and clock multiplication circuitry. The TDC will incorporate either a parallel or high- speed serial interface and will be implemented as an IC in an advanced SiGe BiCMOS technology. Access to such technology is granted to our Company by DOD through the TAPO program. The company anticipates that successful completion of Phase I will result in the design of the systems architecture and schematics of most critical blocks. The fully functional prototype of the TDC ASIC incorporating the FPGA-compatible interface will be fabricated during Phase II, followed by the assembly of a complete system featuring VME interface. The robust reconfigurable TDC will make the proposed system beneficial for different scientific research projects performed by DOE. The developed technique will significantly improve cost-performance characteristics of military and commercial systems including a new generation of radar processing units, space based radar, collision avoiding devices for military and commercial aircrafts, medical proton radiology, positron emission tomography, etc.

* information listed above is at the time of submission.

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