Radiation-Hardened Low-Power ADC for Particle Detectors

Award Information
Agency:
Department of Energy
Branch
n/a
Amount:
$1,006,630.00
Award Year:
2012
Program:
SBIR
Phase:
Phase II
Contract:
DE-FG02-11ER90093
Award Id:
n/a
Agency Tracking Number:
97646
Solicitation Year:
2012
Solicitation Topic Code:
61 a
Solicitation Number:
DE-FOA-0000676
Small Business Information
3580 West Ina Rd, Tucson, AZ, 85741-2276
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
157955597
Principal Investigator:
Esko Mikkola
Dr.
(520) 742-3300
emikkola@ridgetopgroup.com
Business Contact:
Milena Thompson
Dr.
(520) 742-3300
mthompson@ridgetopgroup.com
Research Institution:
Stub




Abstract
Particle detectors for nuclear physics and high energy physics experiments require high performance, high sensitivity digitizers for read-out electronics. Analog-to-digital converters (ADCs) are used in such applications but limit experimental results because of a restrictive combination of speed, resolution, power, and radiation-hardness. Many instruments need very high channel counts, a costly requirement and a very difficult objective to achieve where densely packed electronics generate too much heat. General statement of how this problem or situation is being addressed. This Phase II will result in the design and fabrication of an innovative high-performance, ultra-low-power device that will incorporate 16 ADC channels on a single chip. Using radiation-hardened-by-design (RHBD) techniques and the novel topology developed and verified in Phase I, the ADC chip will be able to provide the linearity and resolution required for use in a wide range of experimental instrumentation at HEP facilities like RHIC and LHC, and in nuclear physics labs at Jefferson Lab, Oak Ridge, and others, while also lowering costs because of the high degree of channel density. What was done in Phase I? Phase I saw the design, development, and simulation of a behavioral model of the complete ADC, along with transistor-level designs of key subcircuits, including operational transconductance amplifiers (OTA), a high-speed comparator, a radiation-tolerant bandgap voltage reference (BGR), a bootstrapped high-linearity sampling switch, and a complete 2.5- bit pipeline stage. This work validated the feasibility of the overall ADC design approach. What is planned for the Phase II project? The Phase II ADC design will lead to a design and fabrication of a chip encompassing an array of 16 ADC channels, each meeting key functionality goals, including 40 MS/s sampling rate, 12-bits resolution at 10.5 11.0 effective number of bits (ENOB), and a very low power dissipation of 12 mW / channel. It will also exceed the required level of TID hardness of 3.5Mrad (Si) as well as achieve extreme tolerance to other radiation effects (e.g., neutron fluencies, SEUs, SEFIs). Commercial Applications and Other Benefits: High performance ADCs hardened to extreme levels of radiation are key components of the LHC experiment, the largest scientific experiment ever constructed. Hundreds of thousands of qualified ADCs will be needed for one detector instrument alone. The currently used ADCs at LHC will be changed to more radiation tolerant and less power consuming ADCs during the upgrade process to High Luminosity Hadron Collider (HL-LHC). Tens of thousands of new radiation hardened, low-power ADCs have been planned to be used in the upgraded Relativistic Heavy Ion Collider (RHIC) as well. Another scientific application for this ADC is NASAs flagship mission to the Jovian moon Europa, as the radiation levels require this type of device. The ADC can be used in defense applications, such as missile control, and federal and commercial space applications. Medical imaging is another application for the ADC

* information listed above is at the time of submission.

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