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Topic 61: Wafer-Scale Geiger-mode Silicon Photomultiplier Arrays Fabricated Using Domestic CMOS Fab

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-FG02-11ER90164
Agency Tracking Number: 97647
Amount: $993,419.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: 61 a
Solicitation Number: DE-FOA-0000676
Solicitation Year: 2012
Award Year: 2012
Award Start Date (Proposal Award Date): 2012-08-08
Award End Date (Contract End Date): 2014-08-07
Small Business Information
15985 NW Schendel Avenue
Beaverton, OR 97006-6703
United States
DUNS: 124348652
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Vinit Dhulla
 (971) 223-5646
Business Contact
 George Williams
Title: Mr.
Phone: (971) 223-5646
Research Institution

There is a need for developing a high-performance Geiger-mode avalanche photodiode (Gm-APD) array design, which can be fabricated using a domestic, high-volume commercial CMOS process on 200mm or greater wafers. Most of todays silicon photomultipliers (SiPMs) and single photon avalanche photodiodes (SPADs) are fabricated using dedicated fabs with custom processes. These designs also have variable breakdown voltage, high dark count rates, high after-pulsing, high cross talk, and limited detector quantum efficiency. Unfortunately, large scale commercial CMOS processes are antithetical to fabricating high-performance imaging devices, especially Gm-APDs, which require substrates and doping profiles compatible with the high electric fields necessary to sustain carrier avalanche. Low cost methods are needed to fabricate wafer-scale SiPMs and SPADs using high volume, domestic CMOS fabs. Silicon Gm-APD arrays will be designed for fabrication on a commercial CMOS fab. Building upon previous experience, devices will be modeled in 3D CAD tools, and a series of designed experiments will be performed to determine a design that can maintain high performance over large areas. Provisions for 3D stacking will be included. A high density, deeply-depleted, Gm-APD (SPAD and SiPM) architectures and were designed, optimized and an experimental lot with designed experiments was taped out for fabrication at domestic CMOS.fab. Si Gm-APD device architecture will be optimized for fabrication using a domestic commercial, large volume, 200mm CMOS process. The devices will be reliability tested, and sample device wafers will be supplied to DOE for integration with application-specific read out integrated circuits (ROICs) Commercial Applications and Other Benefits: The innovation will enable detectors for a wide range of applications including high-energy and nuclear physics, homeland security detection, medical imaging and scanning, time-of-flight measurement, SPECT, astronomy, and astrophysics.

* Information listed above is at the time of submission. *

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