SBIR Phase I: Creating Delay-tolerant, Asynchronous Network Interfaces
National Science Foundation
Agency Tracking Number:
Solicitation Topic Code:
Small Business Information
10176 Corporate Square Drive, Suite 200, St. Louis, MO, 63132-2924
Socially and Economically Disadvantaged:
AbstractThis Small Business Innovation Research (SBIR) Phase I project addresses a growing problem in integrated circuit (IC) system-on-chip (SoC) products. Each such product may have billions of transistors and a feature size of less than the wavelength of visible light. Modern semiconductor processes bring new challenges to IC fabrication because of significantly increased transistor variability and the need to greatly reduce power dissipation. Blendics has developed a wrapper technology that makes each SoC subsystem appear as if it were asynchronous and independent of its neighbors, thereby reducing the undesirable effects of parameter variability and enabling dynamic power reduction techniques. However, the use of manual design methods for these wrappers is inadequate. The goal of this research is to automate this design task making the widespread use of these wrappers economically attractive and still capable of overcoming the inevitable process variability challenges. The proposed research blends asynchronous and synchronous design techniques in order to retain the advantages of conventional tools while avoiding their disadvantages. Results will be a design-automation tool that generates a subsystem?s wrapper from its circuit specification. Success will be achieved if this tool generates wrappers for a broad variety of subsystems with a minimum of additional designer effort. The broader impact/commercial potential of this project arises from the fact that SoC technology finds use in phones, entertainment products, health-care devices, automotive equipment, computers and many other applications that abound in modern life. An individual SoC may be seductively inexpensive in production, but the cost to design and fabricate the first copy of an advanced, custom SoC is today approximately $85 million US dollars. This cost is bound to rise as new semiconductor processes are introduced. Much of this design cost is associated with overcoming the timing constraints associated with global connectivity among the subsystems. This is the problem that the proposed wrapper technology addresses. Thus, developing a world-wide standard for creating a network-on-chip is a significant opportunity in the $1.7B silicon intellectual-property business sector. Such a standard could overcome the serious technical problem the semiconductor industry faces as it moves forward. In the absence of a good solution to this problem of process variability, the cost of the first copy of an SoC is likely to become so high that only the highest volume products will make good business sense. As a result, public access may be denied important SoC products in medical and safety applications.
* information listed above is at the time of submission.