SBIR Phase I: Self-Compensating Ultra-Wideband Direct Digital-to-RF D/A Converter
National Science Foundation
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Small Business Information
17217 Waterview Parkway, Suite 1.202H, Dallas, TX, 75252
Socially and Economically Disadvantaged:
AbstractThis Small Business Innovation Research Phase I project attempts to overcome fundamental limitations that are currently inhibiting the realization of much needed low-cost high-performance digital-to-analog converters (DACs), which can accommodate the wide bandwidths of current and future communication systems, software-defined-radios (SDR), and a wide range of other applications. The focus of this research is the development of circuitry and signal processing and control algorithms that would effectively address impairments experienced in a complementary-metal-oxide-semiconductor (CMOS) implementation of a novel DAC topology designed to accommodate ultra-wide bandwidths. While the CMOS fabrication process may be tailored for digital processors and memory, it is a most challenging environment for the design of high-performance, wide dynamic range analog circuitry. The solutions being developed essentially provide the DAC with ?self-healing? capabilities that allow it to overcome inevitable impairments such as device mismatches, non-linearities, and timing misalignments. Preliminary results indicate the validity of the proposed architectures and approaches and it is anticipated that a fabrication-ready design will result from the Phase 1 research. The involvement of researchers and PhD candidates from academia in this research allows them exposure into most challenging research topics that are of great interest to the semiconductor industry. The broader impact/commercial potential of this project is in allowing ultra-high-performance data-conversion capabilities to be integrated into low-cost CMOS system-on-chip (SoC) solutions that are widely used in commercial applications of various types ranging from communications and multimedia to instrumentation. In particular, the technology being developed will allow for the integration and low-cost realization of this most critical function in a true SDR. The proposed innovation, targeting the self-sufficient-compensation for the effects of inevitable impairments, such as fabrication-process variations, mismatches, non-linearities, and timing misalignments, through the employment of novel built-in calibration and compensation circuitry and algorithms, will allow integrated DACs to deliver ultra-high performance (e.g., 16-bit resolution at rates above 10GHz) without requiring costly testing at fabrication, production-yield losses, laser trimming, or any other consequence of traditional design and manufacturing of high-performance analog integrated circuits. The approach to be developed has a broader impact on chip manufacturing, as these impairments represent limiting factors in other functions as well. As an enabling technology, the proposed innovation can potentially greatly increase the size of the existing market for data converters, currently at $3B, and allow for various new consumer applications where wide bandwidths of operation are needed and cost is a constraint.
* information listed above is at the time of submission.