SBIR Phase I: Automatic Scalable Architectural Validation for Microprocessors

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 1215131
Agency Tracking Number: 1215131
Amount: $149,908.00
Phase: Phase I
Program: SBIR
Awards Year: 2012
Solicitation Year: 2012
Solicitation Topic Code: EI
Solicitation Number: N/A
Small Business Information
330 E. Liberty St., Lower Levelm, Ann Arbor, MI, 48104-2274
DUNS: 832606417
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Zaher Andraus
 (734) 272-8231
Business Contact
 Zaher Andraus
Phone: (734) 272-8231
Research Institution
This Small Business Innovation Research Phase I Project addresses the challenge of automating and scaling formal equivalence verification between architectural ESL/TLM SystemC models and RTL Verilog models for microprocessors and ASIC microcontrollers. The complexity of industrial processors, together with the differences in semantics of SystemC and Verilog, create a significant modeling gap that makes it infeasible to verify RTL Verilog implementations against their SystemC specification models. This gap impedes the progression currently taking place in EDA, wherein designers are moving upwards in the abstraction level for modeling and verifying hardware designs. Our formal equivalence verification technology will allow automatically obtaining RTL from ESL models using high-level synthesis tools, and formally verifying the correctness of the resulting models against the specification models. It will also allow manually written RTL models to be verified against ESL models originally created for architectural simulation. Expected challenges include overcoming the spatial and temporal modeling gaps, and verifying equivalence for an unlimited depth using finite equivalence formulations. By end of project, we anticipate to prototype a software program that will discover unintended behavior in microprocessor designs by ARM with respect to the reference architecture, or prove the lack of any bugs, with modest computational resources. Functional verification of microprocessor designs remains a key challenge for the industry due to exponentially growing verification costs - typically>50% of a design budget. Formal verification has potential to reduce these costs, however existing formal technology can only handle small RTL blocks and is only used by a handful of formal domain experts. With the industry shifting towards larger design blocks and higher-level ESL languages such as SystemC, a turn-key tool such as ours is necessary to bridge the ESL/RTL verification gap and addresses the needs of design and verification engineers who do not necessarily have formal domain expertise. Our target market includes both the integrated design manufacturing and fabless ASIC/SoC suppliers. A typical customer would be an ASIC design company looking to lower verification costs, decrease time-to-market, and reduce the risks of discovering errors during post-silicon verification or post-production. Formal semiconductor verification tools such as ours play an especially vital role in mission-critical semiconductor design markets such as ASICs for medical equipment, high-availability sensors, and automotive semiconductors. Our long-term goal is to make formal verification technologies scalable and directly usable by designers at higher abstraction levels, enabling exponential growth in design complexity without exponential growth in verification cost.

* Information listed above is at the time of submission. *

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