SBIR Phase I: On Demand Verification for Analog Integrated Circuits

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 1215450
Agency Tracking Number: 1215450
Amount: $150,000.00
Phase: Phase I
Program: SBIR
Awards Year: 2012
Solicitation Year: 2012
Solicitation Topic Code: EI
Solicitation Number: N/A
Small Business Information
Zipalog, Inc.
850 Central Parkway East, Suite 160, Plano, TX, 75074-5553
DUNS: 968362587
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Michael Krasnicki
 (214) 418-3347
Business Contact
 Michael Krasnicki
Phone: (214) 418-3347
Research Institution
This Small Business Innovation Research Phase I project proposes an on-demand verification (ODV) facility for analog / mixed-signal application (A/MS) specific integrated circuits (ASICs). The technology innovation is a virtualized cloud-based verification platform that supports all aspects of A/MS ASIC verification for integrated circuit design centers, including behavioral modeling, test bench management, simulation planning, simulation farming, and data mining. The proposed ODV system scales with ASIC complexity and design staff expansion by leveraging cloud computing resources. More importantly, the proposed verification resources can be scaled down once verification tasks are complete, creating opportunities for small design centers to create high quality designs with competitive cost structure for design operations. The initial proof-of-concept design system will be equipped with open source EDA design, modeling, and verification software tools. The modularity inherent in the proposed verification platform will also support the installation of best-in-class commercial partner software solutions and their use in ASIC verification activities by subscribers to the ODV facility. The broader impact/commercial potential of this project is to improve the competitiveness of U.S. semiconductor industry by reducing A/MS design verification cycle time, improving first pass design success and reducing time-to-market. The complexity of A/MS ASIC design has aggressively followed Moore?s law, but innovations in design verification have not. Small, fabless analog design centers in particular struggle to compete in complex design creation given the existing EDA licensing model. Equipping a small design team with the proper verification and analysis tools, for example, is financially equivalent to quadrupling the staff. The results of this research work will lower barriers to entry and innovation for small and emerging companies by providing a scalable verification service without the onerous burden of additional software licensing costs and infrastructure overhead. In addition, the ODV system enables more collaborative innovation among the market players through a cloud-based platform. This would materially benefit the existing semiconductor market participants and open the door for new participants.

* information listed above is at the time of submission.

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