SBIR Phase II: Integrated Circuit Yield and Quality Improvement thru Test Data Analysis

Award Information
National Science Foundation
Award Year:
Phase II
Agency Tracking Number:
Solicitation Year:
Solicitation Topic Code:
Solicitation Number:
Small Business Information
TestWorks, Inc.
1511 Brimfield Drive, Sewickley, PA, 15143-0000
Hubzone Owned:
Minority Owned:
Woman Owned:
Principal Investigator:
Ronald Blanton
(412) 607-3216
Business Contact:
Ronald Blanton
(412) 607-3216
Research Institution:

This Small Business Innovation Research (SBIR) Phase II project develops an automated, software-based analysis methodology that enables yield and quality improvement of integrated circuits (ICs) through information extraction from test measurement data. Deriving actionable information from test data is a challenging task due to lack of software that automatically correlates test measurement data obtained from failing ICs and their physical IC-design description (i.e., the layout). Maximizing knowledge extraction is accomplished by a new software-based diagnosis technique that uses in conjunction the logical and layout descriptions, in addition to the measured test data, to identify at the nanometer scale, the precise location and type of defects within non-working ICs. The project also develops software-based statistical methods that find commonalities among the defects characterized within failing ICs. The combination of improved diagnosis and commonality analyses means that the root-causes for failure can be quickly found and passed on to designers, process engineers, and test engineers to guide remedy selection and deployment. The broader impact/commercial potential of this project centers on continuing the advancement of the US semiconductor industry which is vital to both Homeland Security and the general advancement of society as a whole. There is significant commercial opportunity in supplying test data analysis on a per-design basis to Integrated Circuit (IC) producers that enables rapid improvement in yield and quality through feedback from manufacturing testing. The potential impact is tremendous since specific, pertinent information is fed back to both designers and manufacturers about how and why ICs fail. Chip designers will use this information to improve design rules for producing high-yielding and ultra-reliable ICs. Chip manufacturers will use this information to fine-tune their fabrication processes to maximize yield and performance, and optimize their test methodologies to ensure quality meets customer demands. It is also anticipated that this technology will also spur further research and broaden the scope of research in universities.

* information listed above is at the time of submission.

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