Dual Speed Read Out Integrated Circuit (ROIC)

Award Information
Agency:
Department of Defense
Branch
n/a
Amount:
$150,000.00
Award Year:
2012
Program:
SBIR
Phase:
Phase I
Contract:
H92222-12-P-0066
Award Id:
n/a
Agency Tracking Number:
S121-003-0112
Solicitation Year:
2012
Solicitation Topic Code:
SOCOM12-003
Solicitation Number:
2012.1
Small Business Information
240 W. Elmwood Dr., Suite 2010, Dayton, OH, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
141943030
Principal Investigator:
ToddGrimes
Project Manager
(937) 433-2886
tgrimes@Rnet-Tech.com
Business Contact:
V.Nagarajan
President
(937) 433-2886
vnagarajan@Rnet-Tech.com
Research Institute:
Stub




Abstract
This SBIR requires the development of an innovative dual speed ROIC (DSROIC) architecture, mated to a detector array within the band of interest and with suitable response speed. According to the solicitation, this effort will establish a DSROIC concept capable of performing conventional staring imaging at video frame rates, while simultaneously being able to process and detect each frame at a higher rate. The solicitation further states that the ability to smartly integrate higher frame rates will provide an overall enhanced image quality and provide an automatic integration time providing the user enhanced image quality. In addition to the greatly increased frame rate, desired features include specialized functionality that will allow for windowing/binning, zoom, autonomous signal processing, programmable frame time, programmable conversion gain, and analog to digital conversion per pixel. RNET is proposing to develop a real-time, digital DSROIC architecture with enhanced performance that will provide the much needed improvements in future FPAs. The envisioned DSROIC architecture focuses on the combination of the front-end of split channel pixel cell design, embedded analog-to-digital conversion (ADC), and programmable features.

* information listed above is at the time of submission.

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