Low Cost Universal Reliability System On-A-Chip for Multi-Channel Characterization
Department of Defense
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4380 Viewridge Avenue, Suite D, San Diego, CA, -
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AbstractABSTRACT: As more and more RF systems push for higher frequency and faster bit-rate application, the capability to perform RF reliability testing on new devices and integrated modules will have a drastic impact on technology insertion, standards for circuit and process evaluation, and product application assurance. Indeed, system reliability concerns are imperative to future military sensor, electronic warfare, and communication systems. In essence there remains one primary and significant issue that limits the widespread implementation of RF reliability assessment on a large scale. The issue is cost. One way to reduce cost is to integrate functions in fewer boxes or packages. Possible implementation architectures would most probably combine a system in-a-package (SIP) mother-board with a group of system-on-chip (SOC) monolithic building blocks specific to frequency, power level, and DC bias/sensing requirements. By segmenting circuit functions by semiconductor technology-attributes it is possible to create universal"building-block"monolithic devices. This Phase I effort will focus on implementing a universal reliability system configuration that has a goal of significantly reducing the cost per site of RF accelerated life test systems. BENEFIT: Development of low cost Power Amplifier Module reliability test system. Applicable to RF-HTOL and performance degradation assessment. Turn-key, automated accelerated life test system platform for technology and device reliability assessment.
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