Techniques for Co-Site Interference Mitigation in Phased Arrays

Award Information
Agency:
Department of Defense
Branch
n/a
Amount:
$742,867.00
Award Year:
2012
Program:
SBIR
Phase:
Phase II
Contract:
N66001-12-C-5205
Agency Tracking Number:
N101-104-0924
Solicitation Year:
2010
Solicitation Topic Code:
N101-104
Solicitation Number:
2010.1
Small Business Information
Pharad LLC
797 Cromwell Park Drive, Suite V, Glen Burnie, MD, -
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
137352246
Principal Investigator:
Dalma Novak
Vice President
(410) 590-3333
dnovak@pharad.com
Business Contact:
Austin Farnham
President
(410) 590-3333
afarnham@pharad.com
Research Institution:
Stub




Abstract
In this Phase II program Pharad will build on successful Phase I feasibility studies of our two innovative approaches for mitigating the effects of co-site interference in submarine phased array communication systems. We will realize prototype hardware that will extend the co-site interference mitigation performance achieved in Phase I while conforming to the physical/spatial and environmental constraints of the intended submarine phased array antenna system. Our proposed co-site mitigation technologies comprise a passive RF isolation circuit that provides electromagnetic isolation between a closely located narrowband transmit array and wideband receive array and a photonic interference cancellation technique that can be easily integrated with a fiber-optic RF signal distribution architecture for transmission of the phased array aperture signals. Our co-site mitigation technologies do not require any modification of the phased array antenna elements, can work together to maximize the amount of co-site interferer suppression, and can be architected to minimize the impact on SWaP (size, weight, and power). During the Phase II program we will carry out extensive design, fabrication, and performance testing activities. Our developed prototype co-site mitigation technologies will then be demonstrated and experimentally validated in representative hardware demonstrator test platforms.

* information listed above is at the time of submission.

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